Datasheet

 2012 Microchip Technology Inc. Preliminary DS41639A-page 75

PIC16(L)F1454/5/9

5.9 Register Definitions: Oscillator Control

R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-0/0 R/W-0/0

SPLLEN SPLLMULT IRCF<3:0> SCS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words = 1:

SPLLEN bit is ignored. PLL is always enabled (subject to oscillator requirements)

If PLLEN in Configuration Words =

1 = PLL is enabled

0 = PLL is disabled

bit 6 SPLLMULT: Software PLL Multiplier Select bit

1 = 3x PLL is enabled

0 = 4x PLL is enabled

bit 5-2 IRCF<3:0>: Internal Oscillator Frequency Select bits

1111 = 16 MHz or 48 MHz HF (see Section 5.2.2.1 “HFINTOSC”)

1110 = 8 MHz or 24 MHz HF (3x PLL) or 32 MHz HF (4x PLL) (see Section 5.2.2.1 “HFINTOSC”)

1101 =4MHz

1100 =2MHz

1011 =1MHz

1010 =500kHz

(1)

1001 =250kHz

(1)

1000 =125kHz

(1)

0111 = 500 kHz (default upon Reset)

0110 =250kHz

0101 =125kHz

0100 =62.5kHz

001x =31.25kHz

(1)

000x =31kHz LF

bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block

01 = Secondary oscillator

00 = Clock determined by FOSC<2:0> in Configuration Words.

Note 1: Duplicate frequency derived from HFINTOSC.