Datasheet

PIC16(L)F1454/5/9
DS41639A-page 54 Preliminary  2012 Microchip Technology Inc.
REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
LVP
DEBUG
(3)
LPBOR BORV STVREN PLLEN
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 U-1 U-1 R/P-1 R/P-1
PLLMULT USBLSCLK CPUDIV<1:0>
— —WRT<1:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 13 LVP: Low-Voltage Programming Enable bit
(1)
1 = Low-voltage programming enabled
0 = High-voltage on MCLR
must be used for programming
bit 12 DEBUG: In-Circuit Debugger Mode bit
(3)
1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11
LPBOR
: Low-Power BOR Enable bit
1 = Low-Power Brown-out Reset is disabled
0 = Low-Power Brown-out Reset is enabled
bit 10 BORV: Brown-out Reset Voltage Selection bit
(2)
1 = Brown-out Reset voltage (Vbor), low trip point selected
0 = Brown-out Reset voltage (
Vbor, high trip point selected
bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 8 PLLEN: PLL Enable bit
1 = PLL is enabled
0 = PLL is disabled
bit 7 PLLMULT: PLL Multiplier Selection bit
1 = 3x PLL Output Frequency is selected
0 = 4x PLL Output Frequency is selected
bit 6 USBLSCLK: USB Low-Speed Clock Selection bit
1 = USB Clock divide-by 8 (48 MHz system input clock expected)
0 = USB Clock divide-by 4 (24 MHz system input clock expected)
bit 5-4 CPUDIV<1:0>: CPU System Clock Selection bits
11 = CPU system clock divided by 6
10 = CPU system clock divided by 3
01 = CPU system clock divided by 2
00 = No CPU system clock divide
bit 3-2 Unimplemented: Read as ‘1’
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits
8 kW Flash memory
:
11 = Write protection off
10 = 000h to 01FFh write-protected, 0200h to 1FFFh may be modified
01 = 000h to 0FFFh write-protected, 1000h to 1FFFh may be modified
00 = 000h to 1FFFh write-protected, no addresses may be modified
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: See Vbor parameter for specific trip point voltages.
3: The DEBUG
bit in Configuration Words is managed automatically by device development tools including
debuggers and programmers. For normal device operation, this bit should be maintained as a '1'.