Datasheet
2012 Microchip Technology Inc. Preliminary DS41639A-page 39
PIC16(L)F1454/5/9
Bank 2
10Ch LATA — —LATA5LATA4— — — — --xx ---- --uu ----
10Dh LATB
(1)
LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- uuuu ----
10Eh LATC LATC7
(1)
LATC6
(1)
LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu
10Fh
— Unimplemented — —
110h
— Unimplemented — —
111h CM1CON0
(2)
C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100
112h CM1CON1
(2)
C1INTP C1INTN C1PCH<1:0> — C1NCH<2:0> 0000 -000 0000 -000
113h CM2CON0
(2)
C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 0000 -100 0000 -100
114h CM2CON1
(2)
C2INTP C2INTN C2PCH<1:0> — C2NCH<2:0> 0000 -000 0000 -000
115h CMOUT
(2)
— — — — — —MC2OUT MC1OUT---- --00 ---- --00
116h BORCON SBOREN BORFS
— — — — — BORRDY 10-- ---q uu-- ---u
117h FVRCON
(2)
FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
118h DACCON0
(2)
DACEN — DACOE1 DACOE2 DACPSS<1:0> — — 0-00 00-- 0-00 00--
119h DACCON1
(2)
— — — DACR<4:0> ---0 0000 ---0 0000
11Ah
to
11Ch
— Unimplemented — —
11Dh APFCON CLKRSEL SDOSEL
(1)
SSSEL
—
T1GSEL P2SEL
(1)
— —
000- --00 000- --00
11Eh
— Unimplemented — —
11Fh
— Unimplemented — —
Bank 3
18Ch ANSELA
(2)
— — — ANSA4 — — — — ---1 ---- ---1 ----
18Dh ANSELB
(1)
— — ANSB5 ANSB4 — — — — --11 ---- --11 ----
18Eh ANSELC
(2)
ANSC7
(1)
ANSC6
(1)
— — ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111
18Fh
— Unimplemented — —
190h
— Unimplemented — —
191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 0000
192h PMADRH
—
(2)
Flash Program Memory Address Register High Byte 1000 0000 1000 0000
193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h PMDATH
— — Flash Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h PMCON1
—
(2)
CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000
196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 0000
197h VREGCON
(1)
——————VREGPMReserved ---- --01 ---- --01
198h
— Unimplemented — —
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000
19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL
— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addres
s
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16(L)F1459 only.
2: PIC16(L)F1455/9 only.
3: Unimplemented, read as ‘1’.