Datasheet

PIC16(L)F1454/5/9
DS41639A-page 378 Preliminary  2012 Microchip Technology Inc.
TABLE 29-12: SPI MODE REQUIREMENTS
Param
No.
Symbol Characteristic Min. Typ† Max. Units Conditions
SP70* TSSL2SCH,
T
SSL2SCL
SS
 to SCK or SCK input TCY ——ns
SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns
SP72* T
SCL SCK input low time (Slave mode) TCY + 20 — — ns
SP73* T
DIV2SCH,
T
DIV2SCL
Setup time of SDI data input to SCK edge 100 — — ns
SP74* T
SCH2DIL,
T
SCL2DIL
Hold time of SDI data input to SCK edge 100 — — ns
SP75* T
DOR SDO data output rise time 3.0-5.5V — 10 25 ns
1.8-5.5V — 25 50 ns
SP76* TDOF SDO data output fall time — 10 25 ns
SP77* T
SSH2DOZSS to SDO output high-impedance 10 — 50 ns
SP78* T
SCR SCK output rise time
(Master mode)
3.0-5.5V — 10 25 ns
1.8-5.5V — 25 50 ns
SP79* TSCF SCK output fall time (Master mode) — 10 25 ns
SP80* T
SCH2DOV,
T
SCL2DOV
SDO data output valid after
SCK edge
3.0-5.5V — — 50 ns
1.8-5.5V — — 145 ns
SP81* T
DOV2SCH,
T
DOV2SCL
SDO data output setup to SCK edge Tcy — — ns
SP82* T
SSL2DOV SDO data output valid after SS edge — — 50 ns
SP83* T
SCH2SSH,
T
SCL2SSH
SS
after SCK edge 1.5TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.