Datasheet

PIC16(L)F1454/5/9
DS41639A-page 370 Preliminary  2012 Microchip Technology Inc.
TABLE 29-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
FIGURE 29-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym. Characteristic Min. Typ† Max. Units Conditions
30 TMCLMCLR Pulse Width (low) 2
5
—
—
—
—
s
s
V
DD = 3.3-5V, -40°C to +85°C
V
DD = 3.3-5V
31 T
WDTLP Low-Power Watchdog Timer
Time-out Period
10 16 27 ms VDD = 3.3V-5V,
1:16 Prescaler used
33* T
PWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms
34* T
IOZ I/O high-impedance from MCLR Low
or Watchdog Timer Reset
——2.0s
35 V
BOR Brown-out Reset Voltage
(2)
2.55
1.80
2.70
1.90
2.85
2.11
V
V
BORV = 0
BORV = 1
36* VHYST Brown-out Reset Hysteresis 0 25 50 mV -40°C to +85°C
37* T
BORDC Brown-out Reset DC Response
Time
135sVDD  VBOR
38* VLPOR Low-Power Brown-out 1.8 2.1 2.5 V LPBOR = 1
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1
F and 0.01 F values in parallel are recommended.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1
F and 0.01 F values in parallel are recommended.
T0CKI
T1CKI
40
41
42
45
46
47
49
TMR0 or
TMR1