Datasheet

 2012 Microchip Technology Inc. Preliminary DS41639A-page 369
PIC16(L)F1454/5/9
FIGURE 29-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 29-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
Internal Reset
(1)
Watchdog Timer
33
30
31
34
I/O pins
34
Note 1: Asserted low.
Reset
(1)
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
33
(1)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’.
2 ms delay if PWRTE
= 0 and VREGEN = 1.
Reset
(due to BOR)
V
BOR and VHYST
37