Datasheet

 2012 Microchip Technology Inc. Preliminary DS41639A-page 343
PIC16(L)F1454/5/9
28.2 Instruction Descriptions
ADDFSR Add Literal to FSRn
Syntax: [ label ] ADDFSR FSRn, k
Operands: -32
 k  31
n
 [ 0, 1]
Operation: FSR(n) + k
 FSR(n)
Status Affected: None
Description: The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range 0000h -
FFFFh. Moving beyond these bounds
will cause the FSR to wrap around.
ADDLW Add literal and W
Syntax: [ label ] ADDLW k
Operands: 0
 k  255
Operation: (W) + k
 (W)
Status Affected: C, DC, Z
Description: The contents of the W register are
added to the eight-bit literal ‘k’ and the
result is placed in the W register.
ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0
 f  127
d
0,1
Operation: (W) + (f)  (destination)
Status Affected: C, DC, Z
Description: Add the contents of the W register
with register ‘f’. If ‘d’ is ‘
0’, the result is
stored in the W register. If ‘d’ is ‘
1’, the
result is stored back in register ‘f’.
ADDWFC ADD W and CARRY bit to f
Syntax: [ label ] ADDWFC f {,d}
Operands: 0
 f  127
d
[0,1]
Operation: (W) + (f) + (C)
 dest
Status Affected: C, DC, Z
Description: Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘
0’, the result is
placed in W. If ‘d’ is ‘
1’, the result is
placed in data memory location ‘f’.
ANDLW AND literal with W
Syntax: [ label ] ANDLW k
Operands: 0
 k  255
Operation: (W) .AND. (k)
 (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0
 f  127
d
0,1
Operation: (W) .AND. (f)  (destination)
Status Affected: Z
Description: AND the W register with register ‘f’. If
‘d’ is ‘
0’, the result is stored in the W
register. If ‘d’ is ‘
1’, the result is stored
back in register ‘f’.
ASRF Arithmetic Right Shift
Syntax: [ label ] ASRF f {,d}
Operands: 0
 f  127
d
[0,1]
Operation: (f<7>)
 dest<7>
(f<7:1>)
 dest<6:0>,
(f<0>)
 C,
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘
0’, the result is placed in W. If ‘d’
is ‘
1’, the result is stored back in reg-
ister ‘f’.
register f
C