Datasheet
2012 Microchip Technology Inc. Preliminary DS41639A-page 33
PIC16(L)F1454/5/9
TABLE 3-7: PIC16(L)F1454 MEMORY MAP, BANK 8-23
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh
Core Registers
(Tab l e 3- 2)
480h
48Bh
Core Registers
(Tab l e 3- 2)
500h
50Bh
Core Registers
(Table 3-2)
580h
58Bh
Core Registers
(Table 3-2)
600h
60Bh
Core Registers
(Table 3-2)
680h
68Bh
Core Registers
(Table 3-2)
700h
70Bh
Core Registers
(Table 3-2)
780h
78Bh
Core Registers
(Table 3-2)
40Ch
— 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch —
40Dh
— 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh —
40Eh
—48Eh—50Eh—58Eh—60Eh—68Eh—70Eh—78Eh—
40Fh
—48Fh—50Fh—58Fh—60Fh—68Fh—70Fh—78Fh—
410h
—490h—510h—590h—610h—690h— 710h — 790h —
411h
—491h—511h—591h— 611h PWM1DCL 691h —711h— 791h —
412h
—492h—512h—592h— 612h PWM1DCH 692h — 712h — 792h —
413h
—493h—513h—593h— 613h PWM1CON 693h — 713h — 793h —
414h
—494h—514h—594h— 614h PWM2DCL 694h — 714h — 794h —
415h
—495h—515h—595h— 615h PWM2DCH 695h — 715h — 795h —
416h
—496h—516h—596h— 616h PWM2CON 696h — 716h — 796h —
417h
—497h—517h—597h—617h—697h— 717h — 797h —
418h
—498h—518h—598h—618h—698h— 718h — 798h —
419h
—499h—519h—599h—619h—699h— 719h — 799h —
41Ah
—49Ah—51Ah—59Ah—61Ah—69Ah—71Ah—79Ah—
41Bh
—49Bh—51Bh—59Bh—61Bh—69Bh—71Bh—79Bh—
41Ch
— 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Ch — 79Ch —
41Dh
— 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh —
41Eh
—49Eh—51Eh—59Eh—61Eh—69Eh—71Eh—79Eh—
41Fh
—49Fh—51Fh—59Fh—61Fh—69Fh—71Fh—79Fh—
420h
General
Purpose
Register
80 Bytes
4A0h
General
Purpose
Register
80 Bytes
520h
General
Purpose
Register
80 Bytes
5A0h
General
Purpose
Register
80 Bytes
620h
General
Purpose
Register
48 Bytes
6A0h
Unimplemented
Read as ‘0’
720h
Unimplemented
Read as ‘0’
7A0h
Unimplemented
Read as ‘0’
64Fh
650h
Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h
Common RAM
(Accesses
70h – 7Fh)
4F0h
Common RAM
(Accesses
70h – 7Fh)
570h
Common RAM
(Accesses
70h – 7Fh)
5F0h
Common RAM
(Accesses
70h – 7Fh)
670h
Common RAM
(Accesses
70h – 7Fh)
6F0h
Common RAM
(Accesses
70h – 7Fh)
770h
Common RAM
(Accesses
70h – 7Fh)
7F0h
Common RAM
(Accesses
70h – 7Fh)
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
80Bh
Core Registers
(Tab l e 3- 2 )
880h
88Bh
Core Registers
(Tab l e 3- 2)
900h
90Bh
Core Registers
(Table 3-2)
980h
98Bh
Core Registers
(Table 3-2)
A00h
A0Bh
Core Registers
(Table 3-2)
A80h
A8Bh
Core Registers
(Table 3-2)
B00h
B0Bh
Core Registers
(Table 3-2)
B80h
B8Bh
Core Registers
(Table 3-2)
80Ch
Unimplemented
Read as ‘0’
88Ch
Unimplemented
Read as ‘0’
90Ch
Unimplemented
Read as ‘0’
98Ch
Unimplemented
Read as ‘0’
A0Ch
Unimplemented
Read as ‘0’
A8Ch
Unimplemented
Read as ‘0’
B0Ch
Unimplemented
Read as ‘0’
B8Ch
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh
9EFh
A6Fh
AEFh
B6Fh
BEFh
870h
Common RAM
(Accesses
70h – 7Fh)
8F0h
Common RAM
(Accesses
70h – 7Fh)
970h
Common RAM
(Accesses
70h – 7Fh)
9F0h
Common RAM
(Accesses
70h – 7Fh)
A70h
Common RAM
(Accesses
70h – 7Fh)
AF0h
Common RAM
(Accesses
70h – 7Fh)
B70h
Common RAM
(Accesses
70h – 7Fh)
BF0h
Common RAM
(Accesses
70h – 7Fh)
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.