Datasheet

 2012 Microchip Technology Inc. Preliminary DS41639A-page 303
PIC16(L)F1454/5/9
25.12 Register Definitions: CWG Control
REGISTER 25-1: CWGxCON0: CWG CONTROL REGISTER 0
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0
GxEN GxOEB GxOEA GxPOLB GxPOLA
— —GxCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 GxEN: CWGx Enable bit
1 = Module is enabled
0 = Module is disabled
bit 6
GxOEB: CWGxB Output Enable bit
1 = CWGxB is available on appropriate I/O pin
0 = CWGxB is not available on appropriate I/O pin
bit 5
GxOEA: CWGxA Output Enable bit
1 = CWGxA is available on appropriate I/O pin
0 = CWGxA is not available on appropriate I/O pin
bit 4
GxPOLB: CWGxB Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 3
GxPOLA: CWGxA Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 2-1
Unimplemented: Read as ‘0’
bit 0
GxCS0: CWGx Clock Source Select bit
1 =HFINTOSC
0 =F
OSC