Datasheet

PIC16(L)F1454/5/9
DS41639A-page 292 Preliminary  2012 Microchip Technology Inc.
REGISTER 24-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PWMxDCH<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0
PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits
These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register.
REGISTER 24-3: PWMxDCL: PWM DUTY CYCLE LOW BITS
R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 U-0 U-0
PWMxDCL<7:6>
— — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6
PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits
These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register.
bit 5-0
Unimplemented: Read as ‘0’
TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
PR2 Timer2 module Period Register 199*
PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL
— — — — 291
PWM1DCH PWM1DCH<7:0> 292
PWM1DCL PWM1DCL<7:6>
— — — — — — 292
PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL
— — — — 292
PWM2DCH PWM2DCH<7:0> 292
PWM2DCL PWM2DCL<7:6>
— — — — — — 292
T2CON
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 201
TMR2 Timer2 module Register 199*
TRISA
— — TRISA5 TRISA4
—(1)
—
—(1) —(1)
132
TRISC
TRISC7
(2)
TRISC6
(2)
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 140
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1459 only.