Datasheet

PIC16(L)F1454/5/9
DS41639A-page 282 Preliminary  2012 Microchip Technology Inc.
FIGURE 23-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 23-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 269
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 96
PIE1
TMR1GIE ADIE
(2)
RCIE TXIE SSP1IE — TMR2IE TMR1IE 97
PIR1
TMR1GIF ADIF
(2)
RCIF TXIF SSP1IF — TMR2IF TMR1IF 99
RCREG EUSART Receive Data Register 262*
RCSTA SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 268
SPBRGL BRG<7:0> 270*
SPBRGH BRG<15:8> 270*
TRISC TRISC7
(1)
TRISC6
(1)
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 140
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 267
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
Note 1: PIC16(L)F1459 only.
2: PIC16(L)F1455/9 only.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RCREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)