Datasheet

 2012 Microchip Technology Inc. Preliminary DS41639A-page 19
PIC16(L)F1454/5/9
TABLE 1-4: PIC16(L)F1459 PINOUT DESCRIPTION
Name Function
Input
Type
Output
Type
Description
RA0/D+/ICSPDAT
(3)
RA0 TTL CMOS General purpose I/O.
D+ XTAL XTAL USB differential plus line.
ICSPDAT ST CMOS ICSP™ Data I/O.
RA1/D-/ICSPCLK
(3)
RA1 TTL CMOS General purpose I/O.
D- XTAL XTAL USB differential minus line.
ICSPCLK ST — ICSP Programming Clock.
RA3/V
PP/T1G
(2)
/SS
(2)
/MCLR RA3 TTL — General purpose input with IOC and WPU.
V
PP HV — Programming voltage.
T1G ST — Timer1 Gate input.
SS
ST — Slave Select input.
MCLR
ST — Master Clear with internal pull-up.
RA4/AN3/SOSCO/CLKOUT/
T1G
(1)
/CLKR
(1)
/OSC2
RA4 TTL CMOS General purpose I/O.
AN3 AN — A/D Channel input.
SOSCO XTAL XTAL Secondary Oscillator Connection.
CLKOUT — CMOS F
OSC/4 output.
T1G ST — Timer1 Gate input.
CLKR — CMOS Clock reference output.
OSC2 XTAL XTAL Primary Oscillator connection.
RA5/CLKIN/SOSCI/T1CKI/
OSC1
RA5 TTL CMOS General purpose I/O.
CLKIN CMOS — External clock input (EC mode).
SOSCI XTAL XTAL Secondary Oscillator Connection.
T1CKI ST — Timer1 clock input.
OSC1 XTAL XTAL Primary Oscillator Connection.
RB4/AN10/SDA/SDI RB4 TTL CMOS General purpose I/O.
AN10 AN — A/D Channel input.
SDA I
2
CODI
2
C data input/output.
SDI CMOS — SPI data input.
RB5/AN11/RX/DT RB5 TTL CMOS General purpose I/O.
AN11 AN — A/D Channel input.
RX ST — USART asynchronous input.
DT ST CMOS USART synchronous data.
RB6/SCL/SCK RB6 TTL CMOS General purpose I/O.
SCL I
2
CODI
2
C™ clock.
SCK ST CMOS SPI clock.
RB7/TX/CK RB7 TTL CMOS General purpose I/O.
TX — CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
2
C™ = Schmitt Trigger input with I
2
C
HV = High Voltage XTAL = Crystal levels
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
3: LVP support for PIC18(L)F1XK50 legacy designs.