Datasheet

PIC16(L)F1454/5/9
DS41639A-page 18 Preliminary  2012 Microchip Technology Inc.
RC1/AN5/C1IN1-/
C2IN1-/CWGFLT
/SDA/
SDI/INT/ICSPCLK
RC1 TTL CMOS General purpose I/O.
AN5 AN — A/D Channel input.
C1IN1- AN — Comparator negative input.
C2IN1- AN — Comparator negative input.
CWGFLT
ST — Complementary Waveform Generator Fault input.
SDA I
2
CODI
2
C™ data input/output.
SDI CMOS — SPI data input.
INT ST — External input.
ICSPCLK ST — ICSP™ Programming Clock.
RC2/AN6/DACOUT1/
C1IN2-/C2IN2-/SDO
(1)
RC2 TTL CMOS General purpose I/O.
AN6 AN — A/D Channel input.
DACOUT1 — AN Digital-to-Analog Converter output.
C1IN2- AN — Comparator negative input.
C2IN2- AN — Comparator negative input.
SDO — CMOS SPI data output.
RC3/AN7/DACOUT2/
C1IN3-/C2IN3-/PWM2
(1)
/
SS
(1)
/CLKR
(2)
RC3 TTL CMOS General purpose I/O.
AN7 AN — A/D Channel input.
DACOUT2 — AN Digital-to-Analog Converter output.
C1IN3- AN — Comparator negative input.
C2IN3- AN — Comparator negative input.
PWM2 — CMOS PWM output.
CLC2IN0 ST — Configurable Logic Cell source input.
CLKR — CMOS Clock reference output.
RC4/C1OUT/C2OUT/
CWG1B/TX/CK
RC4 TTL CMOS General purpose I/O.
C1OUT — CMOS Comparator output.
C2OUT — CMOS Comparator output.
CWG1B — CMOS CWG complementary output.
TX — CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
RC5/T0CKI/CWG1A/RX/DT/
PWM1
RC5 TTL CMOS General purpose I/O.
T0CKI ST — Timer0 clock input.
CWG1A — CMOS CWG complementary output.
RX ST — USART asynchronous input.
DT ST CMOS USART synchronous data.
PWM1 — CMOS PWM output.
V
DD VDD Power — Positive supply.
V
SS VSS Power — Ground reference.
V
USB3V3 VUSB3V3 Power — Positive supply for USB transceiver.
TABLE 1-3: PIC16(L)F1455 PINOUT DESCRIPTION (CONTINUED)
Name Function
Input
Type
Output
Type
Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
2
C™ = Schmitt Trigger input with I
2
C
HV = High Voltage XTAL = Crystal levels
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
3: LVP support for PIC18(L)F1XK50 legacy designs.