Datasheet

 2012 Microchip Technology Inc. Preliminary DS41639A-page 15
PIC16(L)F1454/5/9
TABLE 1-2: PIC16(L)F1454 PINOUT DESCRIPTION
Name Function
Input
Type
Output
Type
Description
RA0/D+/ICSPDAT
(3)
RA0 TTL CMOS General purpose I/O.
D+ XTAL XTAL USB differential plus line.
ICSPDAT ST CMOS ICSP™ Data I/O.
RA1/D-/ICSPCLK
(3)
RA1 TTL CMOS General purpose I/O.
D- XTAL XTAL USB differential minus line.
ICSPCLK ST — ICSP Programming Clock.
RA3/V
PP/T1G
(2)
/SS
(2)
/MCLR RA3 TTL — General purpose input with IOC and WPU.
V
PP HV — Programming voltage.
T1G ST — Timer1 Gate input.
SS
ST — Slave Select input.
MCLR
ST — Master Clear with internal pull-up.
RA4/SOSCO/CLKOUT/
T1G
(1)
/SDO
(2)
/CLKR
(1)
/OSC2
RA4 TTL CMOS General purpose I/O.
SOSCO XTAL XTAL Secondary Oscillator Connection.
CLKOUT — CMOS F
OSC/4 output.
T1G ST — Timer1 Gate input.
SDO — CMOS SPI data output.
CLKR — CMOS Clock reference output.
OSC2 XTAL XTAL Primary Oscillator connection.
RA5/CLKIN/SOSCI/T1CKI/
PWM2
(2)
/OSC1
RA5 TTL CMOS General purpose I/O.
CLKIN CMOS — External clock input (EC mode).
SOSCI XTAL XTAL Secondary Oscillator Connection.
T1CKI ST — Timer1 clock input.
PWM2 — CMOS PWM output.
OSC1 XTAL XTAL Primary Oscillator Connection.
RC0/SCL/SCK/ICSPDAT RC0 TTL CMOS General purpose I/O.
SCL I
2
CODI
2
C™ clock.
SCK ST CMOS SPI clock.
ICSPDAT ST CMOS ICSP™ Data I/O.
RC1/SDA/SDI/INT/ICSPCLK RC1 TTL CMOS General purpose I/O.
SDA I
2
CODI
2
C data input/output.
SDI CMOS — SPI data input.
INT ST — External input.
ICSPCLK ST — ICSP Programming Clock.
RC2/SDO
(1)
RC2 TTL CMOS General purpose I/O.
SDO — CMOS SPI data output.
RC3/PWM2
(1)
/SS
(1)
/CLKR
(2)
RC3 TTL CMOS General purpose I/O.
PWM2 — CMOS PWM output.
SS
ST — Slave Select input.
CLKR — CMOS Clock reference output.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I
2
C™ = Schmitt Trigger input with I
2
C
HV = High Voltage XTAL = Crystal levels
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
3: LVP support for PIC18(L)F1XK50 legacy designs.