Datasheet

PIC16(L)F1454/5/9
DS41639A-page 138 Preliminary  2012 Microchip Technology Inc.
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
(1)
TABLE 12-7: SUMMARY OF CONFIGURATION WORD WITH PORTB
REGISTER 12-11: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
WPUB7 WPUB6 WPUB5 WPUB4
— — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 WPUB<7:4>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
bit 3-0 Unimplemented: Read as ‘0’
Note 1: Global WPUEN
bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELB — — ANSB5 ANSB4 — — — — 137
APFCON
CLKRSEL SDOSEL
(1)
SSSEL
—
T1GSEL P2SEL
(1)
— —
130
LATB LATB7 LATB6 LATB5 LATB4
— — — — 137
OPTION_REG
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 185
PORTB RB7 RB6 RB5 RB4
— — — — 136
TRISB TRISB7 TRISB6 TRISB5 TRISB4
— — — — 136
WPUB WPUB7 WPUB6 WPUB5 WPUB4
— — — — 138
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
Note 1: PIC16(L)F1459 only.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
Register
on Page
CONFIG1
13:8
— — FCMEN IESO CLKOUTEN BOREN<1:0> —
52
7:0
CP MCLRE PWRTE WDTE<1:0>
FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTB.