Datasheet

PIC16(L)F1454/5/9
DS41639A-page 134 Preliminary  2012 Microchip Technology Inc.
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
TABLE 12-4: SUMMARY OF CONFIGURATION WORD WITH PORTA
REGISTER 12-6: WPUA: WEAK PULL-UP PORTA REGISTER
U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0
— — WPUA5 WPUA4 WPUA3 — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-3 WPUA<5:3>: Weak Pull-up Register bits
(3)
1 = Pull-up enabled
0 = Pull-up disabled
bit 2-0 Unimplemented: Read as ‘0’
Note 1: Global WPUEN
bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
3: For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELA
(3)
— — —ANSA4— — — — 133
APFCON
CLKRSEL SDOSEL
(2)
SSSEL
—
T1GSEL P2SEL
(2)
— —
130
LATA
— —LATA5LATA4— — — — 133
OPTION_REG
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 185
PORTA
— —RA5RA4RA3—RA1RA0132
TRISA
— — TRISA5 TRISA4 —
(1)
— —
(1)
—
(1)
132
WPUA
— — WPUA5 WPUA4 WPUA3 — — — 134
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1454/5 only.
3: PIC16(L)F1455/9 only.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
Register
on Page
CONFIG1
13:8
— —
FCMEN IESO
CLKOUTEN
BOREN<1:0> —
52
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.