Datasheet

PIC16(L)F1454/5/9
DS41639A-page 100 Preliminary  2012 Microchip Technology Inc.
REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0
OSFIF C2IF C1IF
— BCL1IF USBIF ACTIF —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 C2IF: Numerically Controlled Oscillator Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 C1IF: Numerically Controlled Oscillator Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 Unimplemented: Read as ‘0’
bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2 USBIF: USB Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1 ACTIF: Active Clock Tuning Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 Unimplemented: Read as ‘0’
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.