PIC16(L)F1454/5/9 Data Sheet 14/20-Pin Flash, 8-Bit USB Microcontrollers with XLP Technology 2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16(L)F1454/5/9 14/20-Pin, 8-Bit Flash USB Microcontroller with XLP Technology High-Performance RISC CPU: Extreme Low-Power Management PIC16LF145X with XLP: • • • • • C Compiler Optimized Architecture Only 49 Instructions 14 Kbytes Linear Program Memory Addressing 1024 Bytes Linear Data Memory Addressing Operating Speed: - DC – 48 MHz clock input - DC – 83 ns instruction cycle - Selectable 3x or 4x PLL for specific frequencies • Interrupt Capability with Automatic Context Saving • 16-Level Deep Hardwar
PIC16(L)F145X Peripheral Features: • Up to 14 I/O Pins and Three Input-only Pins: - High current sink/source 25 mA/25 mA - Individually programmable weak pull-ups - Individually programmable Interrupt-On-Change (IOC) pins • Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler • Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode • Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler • Two 10-bit PWM modules • Complementary Waveform Generator
PIC16(L)F145X FIGURE 1: 14-PIN PDIP, SOIC, TSSOP DIAGRAM FOR PIC16(L)F1454/1455 PDIP, SOIC, TSSOP 1 14 RA5 RA4 2 13 VSS RA0/D+/ICSPDAT(1) 12 RA1/D-/ICSPCLK(1) 11 VUSB3V3 10 RC0/ICSPDAT 9 RC1/ICSPCLK 8 RC2 MCLR/VPP/RA3 3 4 RC5 5 RC4 6 RC3 7 PIC16(L)F1454 PIC16(L)F1455 VDD Note 1: LVP support for PIC18(L)F1XK50 legacy designs. 2: See Table 1 and Table 2 for location of all peripheral functions.
PIC16(L)F145X FIGURE 3: 20-PIN PDIP, SOIC, SSOP DIAGRAM FOR PIC16(L)F1459 PDIP, SOIC, SSOP VSS RA0/D+/ICSPDAT(1) 1 20 RA5 2 19 RA4 18 RA1/D-/ICSPCLK(1) MCLR/VPP/RA3 3 4 RC5 5 RC4 6 RC3 7 RC6 8 RC7 9 RB7 10 PIC16(L)F1459 VDD 17 VUSB3V3 16 RC0/ICSPDAT 15 RC1/ICSPCLK 14 RC2 13 RB4 12 RB5 11 RB6 Note 1: LVP support for PIC18(L)F1XK50 legacy designs. 2: See Table 3 for location of all peripheral functions.
PIC16(L)F145X 14-Pin PDIP/SOIC/TSSOP 16-Pin QFN ADC Reference Comparator Timer CWG USB EUSART PWM MSSP Interrupt Basic 14-PIN ALLOCATION TABLE (PIC16(L)F1454) I/O TABLE 1: RA0 13 12 — — — — — D+ — — — IOC ICSPDAT(3) RA1 12 11 — — — — — D- — — — IOC ICSPCLK(3) RA2 — — — — — — — — — — — — — RA3 4 3 — — — T1G(2) — — — — SS(2) IOC MCLR VPP RA4 3 2 — — — SOSCO T1G(1) — — — — SDO(2) IOC CLKOUT OSC2 CLKR(1) RA5 2 1 — — — SO
PIC16(L)F145X 14-Pin PDIP/SOIC/TSSOP 16-Pin QFN ADC Reference Comparator Timer CWG USB EUSART PWM MSSP Interrupt Basic 14-PIN ALLOCATION TABLE (PIC16(L)F1455) I/O TABLE 2: RA0 13 12 — — — — — D+ — — — IOC ICSPDAT(3) RA1 12 11 — — — — — D- — — — IOC ICSPCLK(3) RA2 — — — — — — — — — — — — — RA3 4 3 — — — T1G(2) — — — — SS(2) IOC MCLR VPP RA4 3 2 AN3 — — SOSCO T1G(1) — — — — SDO(2) IOC CLKOUT OSC2 CLKR(1) RA5 2 1 — — —
PIC16(L)F145X 20-Pin PDIP/SOIC/SSOP 20-Pin QFN ADC Reference Comparator Timer CWG USB EUSART PWM MSSP Interrupt Basic 20-PIN ALLOCATION TABLE (PIC16(L)F1459) I/O TABLE 3: RA0 19 16 — — — — — D+ — — — IOC ICSPDAT(3) RA1 18 15 — — — — — D- — — — IOC ICSPCLK(3) RA2 — — — — — — — — — — — — — RA3 4 1 — — — T1G(2) — — — — SS(2) IOC MCLR VPP RA4 3 20 AN3 — — SOSCO T1G(1) — — — — — IOC OSC2 CLKOUT CLKR(1) RA5 2 19 — — — SOSC
PIC16(L)F145X Table of Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 Device Overview ........................................................................................................................................................................ 13 Enhanced Mid-Range CPU ........................................................................................................................................................ 21 Memory Organization .....................
PIC16(L)F145X TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
PIC16(L)F145X NOTES: DS41639A-page 12 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 1.0 DEVICE OVERVIEW The PIC16(L)F1454/5/9 are described within this data sheet. They are available in 14/20-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1454/5/9 devices. Tables 1-2, 1-3 and 1-4 show the pinout descriptions. Reference Table 1-1 for peripherals available per device.
PIC16(L)F1454/5/9 FIGURE 1-1: PIC16(L)F1454/5/9 BLOCK DIAGRAM Program Flash Memory RAM OSC2/CLKOUT OSC1/CLKIN Timing Generation PORTA CPU INTRC Oscillator PORTB(2) (Figure 2-1) MCLR USB EUSART Note DS41639A-page 14 1: 2: CLKR Temp. Indicator(1) PORTC C1(1) C2(1) ADC 10-Bit(1) Timer0 Timer1 Timer2 CWG1(1) FVR(1) PWM1 PWM2 MSSP1 DAC(1) PIC16(L)F1455/9 only. PIC16(L)F1459 only. Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 TABLE 1-2: PIC16(L)F1454 PINOUT DESCRIPTION Name RA0/D+/ICSPDAT(3) RA1/D-/ICSPCLK(3) RA3/VPP/T1G(2)/SS(2)/MCLR RA4/SOSCO/CLKOUT/ T1G(1)/SDO(2)/CLKR(1)/OSC2 RA5/CLKIN/SOSCI/T1CKI/ PWM2(2)/OSC1 RC0/SCL/SCK/ICSPDAT RC1/SDA/SDI/INT/ICSPCLK RC2/SDO(1) RC3/PWM2(1)/SS(1)/CLKR(2) Function Input Type RA0 TTL D+ XTAL Output Type Description CMOS General purpose I/O. XTAL USB differential plus line. ICSPDAT ST CMOS ICSP™ Data I/O. RA1 TTL CMOS General purpose I/O.
PIC16(L)F1454/5/9 TABLE 1-2: PIC16(L)F1454 PINOUT DESCRIPTION (CONTINUED) Name RC4/TX/CK RC5/T0CKI/RX/DT/PWM1 VDD VSS VUSB3V3 Function Input Type RC4 TTL Output Type Description CMOS General purpose I/O. TX — CK ST CMOS USART asynchronous transmit. CMOS USART synchronous clock. RC5 TTL CMOS General purpose I/O. T0CKI ST RX ST DT ST CMOS USART synchronous data. PWM1 — CMOS PWM output. VDD Power VSS Power — Ground reference.
PIC16(L)F1454/5/9 TABLE 1-3: PIC16(L)F1455 PINOUT DESCRIPTION Name RA0/D+/ICSPDAT(3) RA1/D-/ICSPCLK(3) RA3/VPP/T1G(2)/SS(2)/MCLR RA4/AN3/SOSCO/CLKOUT/ T1G(1)/SDO(2)/CLKR(1)/OSC2 RA5/CLKIN/SOSCI/T1CKI/ PWM2(2)/OSC1 RC0/AN4/VREF+/C1IN+/C2IN+/ SCL/SCK/ICSPDAT Function Input Type RA0 TTL D+ XTAL Output Type Description CMOS General purpose I/O. XTAL USB differential plus line. ICSPDAT ST CMOS ICSP™ Data I/O. RA1 TTL CMOS General purpose I/O. D- XTAL XTAL USB differential minus line.
PIC16(L)F1454/5/9 TABLE 1-3: PIC16(L)F1455 PINOUT DESCRIPTION (CONTINUED) Name RC1/AN5/C1IN1-/ C2IN1-/CWGFLT/SDA/ SDI/INT/ICSPCLK RC2/AN6/DACOUT1/ C1IN2-/C2IN2-/SDO(1) RC3/AN7/DACOUT2/ C1IN3-/C2IN3-/PWM2(1)/ SS(1)/CLKR(2) RC4/C1OUT/C2OUT/ CWG1B/TX/CK RC5/T0CKI/CWG1A/RX/DT/ PWM1 Function Input Type RC1 TTL Output Type Description CMOS General purpose I/O. AN5 AN — A/D Channel input. C1IN1- AN — Comparator negative input. C2IN1- AN — Comparator negative input.
PIC16(L)F1454/5/9 TABLE 1-4: PIC16(L)F1459 PINOUT DESCRIPTION Name RA0/D+/ICSPDAT(3) RA1/D-/ICSPCLK(3) RA3/VPP/T1G(2)/SS(2)/MCLR RA4/AN3/SOSCO/CLKOUT/ T1G(1)/CLKR(1)/OSC2 RA5/CLKIN/SOSCI/T1CKI/ OSC1 RB4/AN10/SDA/SDI RB5/AN11/RX/DT RB6/SCL/SCK RB7/TX/CK Function Input Type RA0 TTL D+ XTAL Output Type Description CMOS General purpose I/O. XTAL USB differential plus line. ICSPDAT ST CMOS ICSP™ Data I/O. RA1 TTL CMOS General purpose I/O. D- XTAL XTAL USB differential minus line.
PIC16(L)F1454/5/9 TABLE 1-4: PIC16(L)F1459 PINOUT DESCRIPTION (CONTINUED) Name RC0/AN4/VREF+/C1IN+/C2IN+/ ICSPDAT RC1/AN5/C1IN1-/C2IN1-/ CWGFLT/INT/ICSPCLK RC2/AN6/DACOUT1/ C1IN2-/C2IN2- RC3/AN7/DACOUT2/ C1IN3-/C2IN3-/CLKR(2) RC4/C1OUT/C2OUT/ CWG1B RC5/T0CKI/CWG1A/PWM1 RC6/AN8/SS(1)/PWM2 RC7/AN9/SDO Function Input Type RC0 TTL Output Type Description CMOS General purpose I/O. AN4 AN — VREF+ AN — A/D Channel input. Positive Voltage Reference input.
PIC16(L)F1454/5/9 2.0 ENHANCED MID-RANGE CPU Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability.
PIC16(L)F1454/5/9 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 8.5 “Automatic Context Saving”, for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep.
PIC16(L)F1454/5/9 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - Dual-Port General Purpose RAM - General Purpose RAM - Common RAM TABLE 3-1: The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.
PIC16(L)F1454/5/9 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1454/5/9 PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 3.1.1 There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
PIC16(L)F1454/5/9 3.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.
PIC16(L)F1454/5/9 3.2 Data Memory Organization 3.2.1 The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) Up to 80 bytes of Dual-Port General Purpose RAM (DPR) • 16 bytes of common RAM The core registers contain the registers that directly affect the basic operation.
PIC16(L)F1454/5/9 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC16(L)F1454/5/9 3.3.1 SPECIAL FUNCTION REGISTER 3.3.3 The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.3.
PIC16(L)F1454/5/9 FIGURE 3-2: 7-bit Bank Offset BANKED MEMORY PARTITIONING 3.3.5 DEVICE MEMORY MAPS The memory maps for PIC16(L)F1454/5/9 are as shown in Table 3-8 and Table 3-9. Memory Region 00h 0Bh 0Ch Core Registers (12 bytes) Special Function Registers (20 bytes maximum) 1Fh 20h (1) Dual Port RAM (80 bytes maximum) OR General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh Note 1: If the USB module is disabled, data memory is GPR. If enabled, data memory can be DPR.
PIC16(L)F1454 MEMORY MAP, BANK 0-7 BANK 0 000h BANK 1 080h Core Registers (Table 3-2) Preliminary 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h PORTA — PORTC — — PIR1 PIR2 — — TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON — — — Core Registers (Table 3-2) 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h Dual-Port General Purpose Register 80 Bytes 2012 Microchip Technology Inc
2012 Microchip Technology Inc.
PIC16(L)F1459 MEMORY MAP, BANK 0-7 BANK 0 000h BANK 1 080h Core Registers (Table 3-2) Preliminary 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h PORTA PORTB PORTC — — PIR1 PIR2 — — TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON — — — Core Registers (Table 3-2) 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h Dual-Port General Purpose Register 80 Bytes 06Fh 070h 2012 Microchip
2012 Microchip Technology Inc.
PIC16(L)F1455/9 MEMORY MAP, BANK 8-23 BANK 8 400h BANK 9 480h Core Registers (Table 3-2) Core Registers (Table 3-2) Preliminary 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h — — — — — — — — — — — — — — — — — — — — General Purpose Register 80 Bytes 46Fh 470h Common RAM (Accesses 70h – 7Fh) 47Fh — — — — — — — — — — — — — — — —
2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 TABLE 3-10: PIC16(L)F1454/5/9 MEMORY MAP, BANK 30-31 Bank 31 F8Ch Unimplemented Read as ‘0’ FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD — STKPTR TOSL TOSH = Unimplemented data memory locations, read as ‘0’. DS41639A-page 36 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 3.3.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-11 can be addressed from any Bank.
PIC16(L)F1454/5/9 TABLE 3-12: Addres s SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 00Ch PORTA 00Dh PORTB(1) — — RA5 RA4 RA3 — RA1 RA0 --xx x-xx --xx x-xx RB7 RB6 RB5 RB4 — — — — xxxx ---- xxxx ---- 00Eh PORTC RC7(1) RC6(1) 00Fh — Unimplemented RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx — — 010h — Unimplemented — — 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF
PIC16(L)F1454/5/9 TABLE 3-12: Addres s SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA 10Dh LATB(1) — — LATA5 LATA4 — — — — --xx ---- --uu ---- LATB7 LATB6 LATB5 LATB4 — — — — 10Eh LATC xxxx ---- uuuu ---- LATC7(1) LATC6(1) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 10Fh — Unimplemented xxxx xxxx uuuu uuuu — — 110h — Unimplemented — — 111h CM1CON0(2
PIC16(L)F1454/5/9 TABLE 3-12: Addres s Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Value on POR, BOR Value on all other Resets Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — WPUA5 WPUA4 WPUA3 — — — --11 1--- --11 1--- WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ---- Bank 4 20Ch WPUA 20Dh WPUB(1) 20Eh to 210h — Unimplemented 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSP1ADD ADD<7:0> 0000 0000 0000
PIC16(L)F1454/5/9 TABLE 3-12: Addres s SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — Unimplemented — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 10 50Ch to 51Fh — Bank 11 58Ch to 59Fh — Bank 12 60Ch to 610h — 611h PWM1DCL 612h PWM1DCH 613h PWM1CON0 614h PWM2DCL 615h PWM2DCH 616h PWM2CON0 617h to 61Fh — PWM1DCL<7:6> — — — — — — 00-- ---- 00-- ---- PWM1DCH<7:0> PWM1
PIC16(L)F1454/5/9 TABLE 3-12: Addres s Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 29 E8Ch — Unimplemented — — E8Dh — Unimplemented — — E8Eh UCON — E8Fh USTAT — E90h UIR — SOFIF STALLIF IDLEIF E91h UCFG UTEYE Reserved — — SOFIE BTSEF E92h UIE E93h UEIR E94h UFRMH — E95h RESUME SUSPND — DIR PPBI — -xxx xxx- -uuu uuu- TRNIF ACTVIF UERRIF URSTIF -0
PIC16(L)F1454/5/9 TABLE 3-12: Addres s Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 31 F8Ch — FE3h — FE4h STATUS_ Unimplemented — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Shadow xxxx xxxx uuuu uuuu SHAD FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ — Program Counter Latch High Registe
PIC16(L)F1454/5/9 3.4 PCL and PCLATH 3.4.2 The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC.
PIC16(L)F1454/5/9 3.5 Stack 3.5.1 The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow.
PIC16(L)F1454/5/9 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
PIC16(L)F1454/5/9 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.5.
PIC16(L)F1454/5/9 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS41639A-page 48 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 3.6.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR, DPR and common registers.
PIC16(L)F1454/5/9 3.6.2 3.6.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of DPR or GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the DPR or GPR memory of the next bank.
PIC16(L)F1454/5/9 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers.
PIC16(L)F1454/5/9 4.
PIC16(L)F1454/5/9 REGISTER 4-1: bit 2-0 Note 1: 2: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH: External clock, High-Power mode: on CLKIN pin 110 = ECM: External clock, Medium-Power mode: on CLKIN pin 101 = ECL: External clock, Low-Power mode: on CLKIN pin 100 = INTOSC oscillator: I/O function on OSC1 pin 011 = EXTRC oscillator: RC function connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator on OSC1 and OSC2 pins 001 = XT oscillator: Cryst
PIC16(L)F1454/5/9 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 LVP R/P-1 DEBUG (3) R/P-1 R/P-1 R/P-1 R/P-1 LPBOR BORV STVREN PLLEN bit 13 R/P-1 R/P-1 PLLMULT USBLSCLK bit 8 R/P-1 R/P-1 CPUDIV<1:0> U-1 U-1 — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage pr
PIC16(L)F1454/5/9 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s.
PIC16(L)F1454/5/9 4.6 Device ID and Revision ID The memory location 8005h and 8006h are where the Device ID and Revision ID are stored. See Section 11.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.
PIC16(L)F1454/5/9 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits.
PIC16(L)F1454/5/9 FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FOSC<2:0> 3 SPLLMULT PLLMULT INTOSC CLKIN/ OSC1/ SOSCI/ T1CKI (16 or 8 MHz) Secondary Oscillator (SOSC) SOSC_clk Secondary Clock IRCF<3:0> Postscaler HFINTOSC Start-up Control Logic DS41639A-page 58 1 0 Start-Up OSC 31 kHz Source CPU Divider Primary Clock Active Clock Tuning 16 MHz Internal OSC CPUDIV<1:0> 3x/4x PLL Primary Oscillator (OSC) CLKOUT / OSC2 SOSCO/ T1G SPLLEN PLLEN FSEN 48 MHz INTOSC USB Div
PIC16(L)F1454/5/9 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained within the oscillator module.
PIC16(L)F1454/5/9 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 C1 To Internal Logic Quartz Crystal C2 OSC1/CLKIN RS(1) RF(2) Sleep RP(3) OSC2/CLKOUT A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
PIC16(L)F1454/5/9 5.2.1.4 3x PLL or 4x PLL The oscillator module contains a PLL that can be used with both external and internal clock sources to provide a system clock source. By setting the SPLLMULT bit of the OSCCON register, 3x PLL is selected. By clearing the SPLLMULT bit of the OSCCON register, 4x PLL is selected. The input frequency for the PLL must fall within specifications. See the PLL Clock Timing Specifications in Section 29.0 “Electrical Specifications”.
PIC16(L)F1454/5/9 5.2.1.6 External RC Mode 5.2.2 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. Figure 5-6 shows the external RC mode connections.
PIC16(L)F1454/5/9 5.2.2.2 Internal Oscillator Frequency Adjustment 5.2.2.4 The 16 MHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 5-3). Since all HFINTOSC clock sources are derived from the 16 MHz internal oscillator a change in the OSCTUNE register value will apply to all HFINTOSC frequencies. The default value of the OSCTUNE register is ‘0’. The value is a 7-bit two’s complement number.
PIC16(L)F1454/5/9 5.2.2.5 Internal Oscillator Frequency Selection Using the PLL 5.2.2.6 The Internal Oscillator Block can be used with the PLL associated with the External Oscillator Block to produce a 24 MHz, 32 MHz or 48 MHz internal system clock source. The following settings are required to use the PLL internal clock sources: • The FOSC bits of the Configuration Words must be set to use the INTOSC source as the device system clock (FOSC<2:0> = 100).
PIC16(L)F1454/5/9 FIGURE 5-7: HFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <3:0> =0 0 System Clock 2012 Microchip Techno
PIC16(L)F1454/5/9 5.3 CPU Clock Divider 5.4.1 For low-speed USB Operation, a 24 MHz clock is required for the USB module. To generate the 24 MHz clock, the following Oscillator modes are allowed: The CPU Clock divider allows the system clock to run at a slower speed than the Low/Full-Speed USB module clock, while sharing the same clock source. Only the oscillator defined by the settings of the FOSC bits of the Configuration Words may be used with the CPU clock divider.
PIC16(L)F1454/5/9 TABLE 5-2: HIGH-SPEED USB CLOCK SETTINGS Clock Mode HFINTOSC Clock Frequency 16 MHz 16 MHz PLL Value 3x 3x USBLSCLK CPUDIV<1:0> System Clock Frequency (MHz) 0 11 10 01 00 8 16 24 48 0 11 10 01 00 8 16 24 48 0 11 10 01 00 8 16 24 48 ECH or HS mode 12 MHz 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 5.5 Clock Switching 5.5.3 SECONDARY OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins.
PIC16(L)F1454/5/9 5.6 Two-Speed Clock Start-up Mode 5.6.1 Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.
PIC16(L)F1454/5/9 5.6.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 5.6.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
PIC16(L)F1454/5/9 5.7 Fail-Safe Clock Monitor 5.7.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, RC and secondary oscillator).
PIC16(L)F1454/5/9 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: DS41639A-page 72 Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 5.8 Active Clock Tuning (ACT) 5.8.2 The Active Clock Tuning (ACT) continuously adjusts the 16 MHz Internal Oscillator, using an available external reference, to achieve ± 0.20% accuracy. This eliminates the need for a high-speed, high-accuracy external crystal when the system has an available lower speed, lower power, high-accuracy clock source available. Systems implementing a Real-Time Clock Calendar (RTCC) or a full-speed USB application can take full advantage of the ACT. 5.8.
PIC16(L)F1454/5/9 5.8.5 ACTIVE CLOCK TUNING UPDATE DISABLE When the ACT is enabled, the OSCTUNE register is continuously updated every ACT_clk period. Setting the ACT Update Disable bit can be used to suspend updates to the OSCTUNE register, without disabling the ACT. If the 16 MHz internal oscillator drifts out of the accuracy range, the ACT Status bits will change and an interrupt can be generated to notify the application.
PIC16(L)F1454/5/9 5.
PIC16(L)F1454/5/9 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q U-0 U-0 R-0/q R-0/q SOSCR PLLRDY OSTS HFIOFR — — LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 SOSCR: Secondary Oscillator Ready bit If T1OSCEN = 1: 1 = Secondary oscillator is re
PIC16(L)F1454/5/9 OSCTUNE: OSCILLATOR TUNING REGISTER(1,2) REGISTER 5-3: U-0 R/W-0/0 R/W-0/0 R/W-0/0 — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-0 TUN<6:0>: Frequency Tuning bits 1000000 = Minimum frequency • • • 1111111 = 000000
PIC16(L)F1454/5/9 REGISTER 5-4: ACTCON: ACTIVE CLOCK TUNING (ACT) CONTROL REGISTER R/W-0/0 R/W-0/0 U-0 R/W-0/0 R-0/0 U-0 R-0/0 U-0 ACTEN ACTUD — ACTSRC(1) ACTLOCK — ACTORS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACTEN: Active Clock Tuning Selection bit 1 = ACT is enabled, updates to OSCTUNE ar
PIC16(L)F1454/5/9 6.0 RESETS There are multiple ways to reset this device: • • • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the on-chip Reset circuit is shown in Figure 6-1.
PIC16(L)F1454/5/9 6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC16(L)F1454/5/9 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 6.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
PIC16(L)F1454/5/9 6.4 Low-Power Brown-out Reset (LPBOR) 6.6 The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 6-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 6-2. 6.4.
PIC16(L)F1454/5/9 FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 6.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers.
PIC16(L)F1454/5/9 6.13 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 6-2. 6.
PIC16(L)F1454/5/9 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 81 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 85 STATUS — — — TO PD Z DC C 27 WDTCON — — SWDTEN 110 WDTPS<4:0> Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
PIC16(L)F1454/5/9 7.0 REFERENCE CLOCK MODULE The reference clock module provides the ability to send a divided clock to the clock output pin of the device (CLKR). This module is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application.
PIC16(L)F1454/5/9 7.
PIC16(L)F1454/5/9 TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES Name CLKRCON Legend: Bit 7 Bit 6 Bit 5 CLKREN CLKROE CLKRSLR CONFIG1 Legend: Bit 3 CLKRDC<1:0> Bit 2 Bit 1 Bit 0 Register on Page 88 CLKRDIV<2:0> — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.
PIC16(L)F1454/5/9 NOTES: DS41639A-page 90 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 8.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details.
PIC16(L)F1454/5/9 8.1 Operation 8.2 Interrupts are disabled upon any device Reset.
PIC16(L)F1454/5/9 FIGURE 8-2: INTERRUPT LATENCY Fosc Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP
PIC16(L)F1454/5/9 FIGURE 8-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) PC + 1 — Forced NOP Inst (PC) 0004h Inst (0004h) Forced NOP 0005h Inst (0005h) Inst (0004h) INTF flag is sampled here (every Q1).
PIC16(L)F1454/5/9 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16(L)F1454/5/9 8.
PIC16(L)F1454/5/9 REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 TMR1GIE ADIE(1) RCIE TXIE SSP1IE — TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate
PIC16(L)F1454/5/9 REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 OSFIE C2IE C1IE — BCL1IE USBIE ACTIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrup
PIC16(L)F1454/5/9 REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 TMR1GIF ADIF(1) RCIF TXIF SSP1IF — TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 =
PIC16(L)F1454/5/9 REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 OSFIF C2IF C1IF — BCL1IF USBIF ACTIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is
PIC16(L)F1454/5/9 TABLE 8-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 96 OPTION_REG WPUEN PIE1 TMR1GIE INTEDG TMR0CS TMR0SE (1) ADIE RCIE PSA PS<2:0> TXIE SSP1IE — TMR2IE 185 TMR1IE 97 PIE2 OSFIE C2IE C1IE — BCL1IE USBIE ACTIE — 98 PIR1 TMR1GIF ADIF(1) RCIF TXIF SSP1IF — TMR2IF TMR1IF 99 PIR2 OSFIF C2IF C1IF — BCL1IF USBIF
PIC16(L)F1454/5/9 NOTES: DS41639A-page 102 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 9.0 POWER-DOWN MODE (SLEEP) The Power-Down mode is entered by executing a SLEEP instruction. Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 7. 8. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep.
PIC16(L)F1454/5/9 9.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared.
PIC16(L)F1454/5/9 9.2 Low-Power Sleep Mode 9.2.2 The PIC16F1454/5/9 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F1454/5/9 allows the user to optimize the operating current in Sleep, depending on the application requirements.
PIC16(L)F1454/5/9 9.
PIC16(L)F1454/5/9 10.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC16(L)F1454/5/9 10.1 Independent Clock Source 10.4 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 29.0 “Electrical Specifications” for the LFINTOSC tolerances. 10.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 10-1. 10.2.1 WDT protection is active during Sleep.
PIC16(L)F1454/5/9 TABLE 10-2: WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 10.
PIC16(L)F1454/5/9 TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 Bit 6 OSCCON SPLLEN SPLLMULT PCON STKOVF STKUNF — RWDT STATUS — — — TO WDTCON — — Legend: CONFIG1 Legend: Bit 4 Bit 3 Bit 2 Bit 1 IRCF<3:0> Bit 0 SCS<1:0> RMCLR RI POR PD Z DC WDTPS<4:0> Register on Page 75 BOR 85 C 27 SWDTEN 110 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
PIC16(L)F1454/5/9 11.0 FLASH PROGRAM MEMORY CONTROL 11.1.1 The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs).
PIC16(L)F1454/5/9 TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE Device PIC16(L)F1454/5/9 11.2.1 Row Erase (words) Write Latches (words) 32 32 FIGURE 11-1: READING THE FLASH PROGRAM MEMORY FLASH PROGRAM MEMORY READ FLOWCHART Start Read Operation Select Program or Configuration Memory (CFGS) To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register.
PIC16(L)F1454/5/9 FIGURE 11-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PC +3 PC+3 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here PC + 5 INSTR (PC + 4) INSTR(PC + 3) executed here INS
PIC16(L)F1454/5/9 11.2.2 FLASH MEMORY UNLOCK SEQUENCE FIGURE 11-3: The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing.
PIC16(L)F1454/5/9 11.2.3 ERASING FLASH PROGRAM MEMORY FIGURE 11-4: While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 11-2.
PIC16(L)F1454/5/9 EXAMPLE 11-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2.
PIC16(L)F1454/5/9 11.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts.
7 6 - r10 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 0 7 5 4 PMADRH r9 r8 r7 r6 0 7 PMADRL r5 r4 r3 r2 r1 r0 c3 c2 c1 - 5 0 7 PMDATH 6 - c0 0 PMDATL 8 14 10 Program Memory Write Latches 5 14 Write Latch #0 00h PMADRL<4:0> 14 Write Latch #1 01h Preliminary 14 CFGS = 0 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 FIGURE 11-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config.
PIC16(L)F1454/5/9 EXAMPLE 11-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4.
PIC16(L)F1454/5/9 11.3 Modifying Flash Program Memory FIGURE 11-7: When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC16(L)F1454/5/9 11.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 11-2.
PIC16(L)F1454/5/9 11.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 11-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM.
PIC16(L)F1454/5/9 11.
PIC16(L)F1454/5/9 REGISTER 11-3: R/W-0/0 PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address REGISTER 11-4: U-1(1) PMADRH
PIC16(L)F1454/5/9 REGISTER 11-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1(1) R/W-0/0 R/W-0/0 — CFGS LWLO R/W/HC-0/0 R/W/HC-x/q(2) FREE WRERR R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6
PIC16(L)F1454/5/9 REGISTER 11-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, befo
PIC16(L)F1454/5/9 12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) Read LATx D Some ports may have one or more of the following additional registers.
PIC16(L)F1454/5/9 12.1 Alternate Pin Function The Alternate Pin Function Control register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 12-1. For this device family, the following functions can be moved between different pins. • • • • • CLKR SDO SS T1G P2 These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. 12.
PIC16(L)F1454/5/9 12.3 12.3.1 PORTA Registers EXAMPLE 12-2: DATA REGISTER PORTA is a 5-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).
PIC16(L)F1454/5/9 12.
PIC16(L)F1454/5/9 REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 — — LATA5 LATA4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3-0 Unimplemented: Read as ‘0’ Note
PIC16(L)F1454/5/9 REGISTER 12-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 — — WPUA5 WPUA4 WPUA3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-3 WPUA<5:3>: Weak Pull-up Register bits(3) 1 = Pull-up enabled 0 = Pull-up disab
PIC16(L)F1454/5/9 12.5 12.5.1 PORTB Registers (PIC16(L)F1455/9 only) 12.5.4 DATA REGISTER PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 12-3). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).
PIC16(L)F1454/5/9 12.
PIC16(L)F1454/5/9 REGISTER 12-9: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 LATB7 LATB6 LATB5 LATB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 LATB<7:4>: RB<7:4> Output Latch Value bits(1) bit 3-0 Unimplemented: Read as ‘0’ Note 1: Writes to PORTB
PIC16(L)F1454/5/9 REGISTER 12-11: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 WPUB7 WPUB6 WPUB5 WPUB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3-0 Unimplemented: Read
PIC16(L)F1454/5/9 12.7 12.7.1 PORTC Registers 12.7.4 DATA REGISTER PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 12-13). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1454/5/9 12.
PIC16(L)F1454/5/9 REGISTER 12-14: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u (1) (1) LATC7 LATC6 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared LATC<7:0>: PORTC Output Latch Value bits(1) bit 7-0 Note 1: 2: Writes to POR
PIC16(L)F1454/5/9 NOTES: DS41639A-page 142 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 13.0 INTERRUPT-ON-CHANGE 13.3 The PORTA and PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual port pin, or combination of port pins, can be configured to generate an interrupt.
PIC16(L)F1454/5/9 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) IOCANx D Q4Q1 Q CK Edge Detect R RAx IOCAPx D Data Bus = 0 or 1 Q Write IOCAFx CK D S Q To Data Bus IOCAFx CK IOCIE R Q2 From all other IOCAFx individual Pin Detectors Q1 Q2 Q3 Q4 Q4Q1 DS41639A-page 144 Q1 Q1 Q2 Q2 Q3 Q4 Q4Q1 IOC interrupt to CPU core Q3 Q4 Q4 Q4Q1 Preliminary Q4Q1 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 13.
PIC16(L)F1454/5/9 REGISTER 13-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 — — R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCAF5 IOCAF4 IOCAF3 U-0 R/W/HS-0/0 R/W/HS-0/0 — IOCAF1 IOCAF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-6 Unimplemented: Read as ‘0’ bit 5-3 IO
PIC16(L)F1454/5/9 REGISTER 13-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits 1 = Interrupt
PIC16(L)F1454/5/9 TABLE 13-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 ANSELA(3) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page 133 — — — ANSA4 — — — — GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 96 IOCAF — — IOCAF5 IOCAF4 IOCAF3 — IOCAF1 IOCAF0 146 IOCAN — — IOCAN5 IOCAN4 IOCAN3 — IOCAN1 IOCAN0 145 IOCAP — — IOCAP5 IOCAP4 IOCAP3 — IOCAP1 IOCAP0 145 IOCBF(2) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 147 IOC
PIC16(L)F1454/5/9 14.0 FIXED VOLTAGE REFERENCE (FVR) (PIC16(L)F1455/9 ONLY) The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels.
PIC16(L)F1454/5/9 14.
PIC16(L)F1454/5/9 15.0 TEMPERATURE INDICATOR MODULE (PIC16(L)F1455/9 ONLY) FIGURE 15-1: VDD This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC16(L)F1454/5/9 TABLE 15-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 118 Shaded cells are unused by the temperature indicator module. DS41639A-page 152 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 16.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE (PIC16(L)F1455/9 ONLY) The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC16(L)F1454/5/9 FIGURE 16-1: ADC BLOCK DIAGRAM VDD ADPREF = 00 VREF+ Reserved 00000 Reserved 00001 Reserved 00010 AN3 00011 VREF+/AN4 00100 AN5 00101 AN6 00110 AN7 AN8 00111 01000 AN9 01001 AN10 01010 AN11 Reserved 01011 01100 Reserved 11100 ADPREF = 10 VREF- = VSS VREF+ ref+ refADC 10 GO/DONE ADFM 0 = Left Justify 1 = Right Justify 16 ADON Temp Indicator 11101 DAC FVR Buffer1 11110 VSS ADRESH ADRESL 11111 CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs ar
PIC16(L)F1454/5/9 16.1 ADC Configuration 16.1.4 When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.
PIC16(L)F1454/5/9 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 (2) 200 ns (2) 250 ns (2) Fosc/8 001 400 ns(2) 0.5 s(2) Fosc/16 101 800 ns 1.0 s Fosc/32 1.6 s 010 2.0 s Fosc/64 110 3.2 s 4.0 s FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Legend: Note 1: 2: 3: 4: 1.
PIC16(L)F1454/5/9 16.1.5 INTERRUPTS 16.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC16(L)F1454/5/9 16.2 16.2.1 ADC Operation 16.2.4 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 16.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 16.2.6 “A/D Conversion Procedure”.
PIC16(L)F1454/5/9 16.2.6 A/D CONVERSION PROCEDURE EXAMPLE 16-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16(L)F1454/5/9 16.
PIC16(L)F1454/5/9 REGISTER 16-2: R/W-0/0 ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 — — R/W-0/0 bit 7 R/W-0/0 ADPREF<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified.
PIC16(L)F1454/5/9 REGISTER 16-3: R/W-0/0 ADCON2: A/D CONTROL REGISTER 2 R/W-0/0 — R/W-0/0 R/W-0/0 TRIGSEL<2:0> U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 TRIGSEL<2:0>: Auto-Conversion Trigger Selection bits(1) 000 = No auto-conversion trigg
PIC16(L)F1454/5/9 REGISTER 16-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 16-5: R/W-x
PIC16(L)F1454/5/9 REGISTER 16-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
PIC16(L)F1454/5/9 16.4 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4.
PIC16(L)F1454/5/9 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.
PIC16(L)F1454/5/9 TABLE 16-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC(3) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> Bit 1 Bit 0 GO/DONE ADON ADCON0 — ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> ADCON2 — TRIGSEL<2:0> — — — — ADRESH ADRESL ANSELA(3) ANSELB (2) ANSELC(3) INTCON PIE1 PIR1 TRISA TRISB(2) TRISC FVRCON Legend: Note 1: 2: 3: Register on Page 160 161 162 163, 164 A/D Result Register Low — 163, 164 — — ANSA4 — — — — ANSB5 ANSB4 — — ANSC7(1) ANSC6(1) —
PIC16(L)F1454/5/9 NOTES: DS41639A-page 168 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 17.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE (PIC16(L)F1455/9 ONLY) The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register.
PIC16(L)F1454/5/9 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) VSOURCE+ VDD DACR<4:0> 5 VREF+ R R DACPSS R DACEN R 32 Steps R 32-to-1 MUX R DAC (To Comparator and ADC Module) R DACOUT1 R DACOE1 VSOURCE- DACOUT2 DACOE2 FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS41639A-page 170 DACOUTX Preliminary + – Buffered DAC Output 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 17.4 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 17.5 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 17.
PIC16(L)F1454/5/9 18.0 COMPARATOR MODULE (PIC16(L)F1455/9 ONLY) FIGURE 18-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
PIC16(L)F1454/5/9 FIGURE 18-2: COMPARATOR MODULES SIMPLIFIED BLOCK DIAGRAM CxNCH<2:0> CxON(1) 3 det 0 Reserved CXIN2- 1 MUX 2 (2) CXIN3- 3 FVR Buffer2 4 CXIN1- Set CxIF 0 MUX 1 (2) DAC FVR Buffer2 CxINTN Interrupt det CXPOL CxVN D Cx CxVP CXIN+ CxINTP Interrupt CXOUT MCXOUT Q + EN Q1 CxHYS CxSP async_CxOUT 2 3 CXSYNC CxON CXPCH<1:0> To CWG CXOE TRIS bit CXOUT 0 2 D (from Timer1) T1CLK Q 1 SYNCCXOUT Note 1: 2: When CxON = 0, the Comparator will produce a ‘0’ at the ou
PIC16(L)F1454/5/9 18.2 Comparator Control 18.2.3 Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 18-1) contain Control and Status bits for the following: • • • • • • Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs.
PIC16(L)F1454/5/9 18.3 Comparator Hysteresis 18.5 A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. See Section 29.
PIC16(L)F1454/5/9 18.7 Comparator Negative Input Selection 18.10 Analog Input Connection Considerations The CxNCH<2:0> bits of the CMxCON0 register direct one of the input sources to the comparator inverting input. Note: 18.8 To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers.
PIC16(L)F1454/5/9 FIGURE 18-3: ANALOG INPUT MODEL VDD Rs < 10K Analog Input pin VT 0.6V RIC To Comparator VA CPIN 5 pF VT 0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS = Analog Voltage VA = Threshold Voltage VT Note 1: DS41639A-page 178 See Section 29.0 “Electrical Specifications”. Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 18.
PIC16(L)F1454/5/9 REGISTER 18-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 CxPCH<1:0> U-0 R/W-0/0 R/W-0/0 R/W-0/0 CxNCH<2:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrup
PIC16(L)F1454/5/9 TABLE 18-3: Name ANSELA ANSELC CM1CON0 SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE(3) Bit 7 Bit 6 — — ANSC7 (2) C1ON ANSC6 (2) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — ANSA4 — — — — 133 — — ANSC3 ANSC2 ANSC1 ANSC0 141 C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 179 C2OE C2POL — C2SP C2HYS C2SYNC 179 CM2CON0 C2ON C2OUT CM1CON1 C1NTP C1INTN CM2CON1 C2NTP C2INTN — — — — DACCON0 DACEN — DACOE1 DACOE2 DACCON1 —
PIC16(L)F1454/5/9 NOTES: DS41639A-page 182 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 19.0 TIMER0 MODULE When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The Timer0 module is an 8-bit timer/counter with the following features: • • • • • • Note: 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 19.1.
PIC16(L)F1454/5/9 19.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC16(L)F1454/5/9 19.
PIC16(L)F1454/5/9 NOTES: DS41639A-page 186 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 20.0 TIMER1 MODULE WITH GATE CONTROL • Gate Single-pulse mode • Gate Value Status • Gate Event Interrupt The Timer1 module is a 16-bit timer/counter with the following features: Figure 20-1 is a block diagram of the Timer1 module.
PIC16(L)F1454/5/9 20.1 Timer1 Operation 20.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.
PIC16(L)F1454/5/9 20.3 Timer1 Prescaler 20.5.1 Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 20.
PIC16(L)F1454/5/9 20.6.2 TIMER1 GATE SOURCE SELECTION 20.6.3 Timer1 gate source selections are shown in Table 20-4. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register.
PIC16(L)F1454/5/9 20.7 Timer1 Interrupt 20.8 The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.
PIC16(L)F1454/5/9 FIGURE 20-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 20-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 DS41639A-page 192 N N+1 N+2 N+3 N+4 Preliminary N+5 N+6 N+7 N+8 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 FIGURE 20-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N N+1 Set by hardware on falling edge of T1GVAL Cleared by software 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 FIGURE 20-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS41639A-page 194 N Cleared by software N+1 N+2 N+3 N+4 Set by hardware on falling edge of T1GVAL Preliminary Cleared by software 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 20.
PIC16(L)F1454/5/9 REGISTER 20-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit
PIC16(L)F1454/5/9 TABLE 20-5: Name ANSELA(3) APFCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — — — — 133 CLKRSEL SDOSEL(2) SSSEL — T1GSEL P2SEL(2) — — 130 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 96 PIE1 TMR1GIE ADIE(3) RCIE TXIE SSP1IE — TMR2IE TMR1IE 97 PIR1 TMR1GIF ADIF(3) RCIF TXIF SSP1IF — TMR2IF TMR1IF INTCON TMR1H Holding Register for the Most Significant Byte
PIC16(L)F1454/5/9 NOTES: DS41639A-page 198 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 21.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP module (Timer2 only) See Figure 21-1 for a block diagram of Timer2.
PIC16(L)F1454/5/9 21.1 Timer2 Operation 21.3 The clock input to the Timer2 module is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle.
PIC16(L)F1454/5/9 21.
PIC16(L)F1454/5/9 TABLE 21-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 96 PIE1 TMR1GIE ADIE(1) RCIE TXIE SSP1IE — TMR2IE TMR1IE 97 PIR1 TMR1GIF ADIF(1) RCIF TXIF SSP1IF — TMR2IF TMR1IF PR2 Timer2 Module Period Register 99 199* PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL — — — — 291 PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL — — — — 291 T
PIC16(L)F1454/5/9 22.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 22.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16(L)F1454/5/9 The I2C interface supports the following modes and features: • • • • • • • • • • • • • Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 22-2 is a block diagram of the I2C interface module in Master mode.
PIC16(L)F1454/5/9 FIGURE 22-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPBUF Reg SCL Shift Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPADD Reg Start and Stop bit Detect 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 22.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select.
PIC16(L)F1454/5/9 FIGURE 22-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 22.2.1 SPI MODE REGISTERS The MSSP module has five registers for SPI mode operation.
PIC16(L)F1454/5/9 22.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
PIC16(L)F1454/5/9 22.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 22-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC16(L)F1454/5/9 22.2.4 22.2.5 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPCON1 register.
PIC16(L)F1454/5/9 FIGURE 22-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI SPI Slave #1 SDO General I/O SS SCK SDI SPI Slave #2 SDO SS SCK SDI SPI Slave #3 SDO SS FIGURE 22-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Shift register SSPSR and bit count are reset SSPBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF 2012 Microchip Technology
PIC16(L)F1454/5/9 FIGURE 22-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active FIGURE 22-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
PIC16(L)F1454/5/9 22.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep.
PIC16(L)F1454/5/9 22.3 I2C MODE OVERVIEW FIGURE 22-11: The Inter-Integrated Circuit Bus (I²C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Figure 22-11 shows a typical connection between two processors configured as master and slave devices.
PIC16(L)F1454/5/9 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration.
PIC16(L)F1454/5/9 22.4 I2C MODE OPERATION TABLE 22-2: All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 22.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back.
PIC16(L)F1454/5/9 22.4.5 START CONDITION 22.4.7 The I2C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 22-12 shows wave forms for Start and Stop conditions. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low.
PIC16(L)F1454/5/9 FIGURE 22-13: I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition DS41639A-page 218 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 22.4.9 22.5 ACKNOWLEDGE SEQUENCE The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more.
PIC16(L)F1454/5/9 22.5.2 22.5.2.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPSTAT register is set, or bit SSPOV of the SSPCON1 register is set.
2012 Microchip Technology Inc. Preliminary SSPOV BF SSPIF S 1 A7 2 A6 3 A5 4 A4 5 A3 Receiving Address 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 5 D3 6 D2 7 D1 SSPBUF is read Cleared by software 3 D4 Receiving Data D5 8 9 2 D6 First byte of data is available in SSPBUF 1 D0 ACK D7 4 5 D3 6 D2 7 D1 SSPOV set because SSPBUF is still full. ACK is not sent.
DS41639A-page 222 Preliminary CKP SSPOV BF SSPIF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSPBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPBUF 6 D2 7 D1 SSPOV set because SSPBUF is still full. ACK is not sent.
2012 Microchip Technology Inc.
DS41639A-page 224 Preliminary P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSPBUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCL 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCL When DHEN = 1; on the 8th falling edge of SCL of a
PIC16(L)F1454/5/9 22.5.3 SLAVE TRANSMISSION 22.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave.
DS41639A-page 226 Preliminary P S D/A R/W ACKSTAT CKP BF SSPIF S 1 2 5 6 7 Received address is read from SSPBUF 4 Indicates an address has been received R/W is copied from the matching address byte When R/W is set SCL is always held low after 9th SCL falling edge 3 8 9 Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSPBUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Mast
PIC16(L)F1454/5/9 22.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure 22-19 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
DS41639A-page 228 Preliminary D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
PIC16(L)F1454/5/9 22.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 22.5.5 This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 22-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle.
DS41639A-page 230 Preliminary CKP UA BF SSPIF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCL is held low If address matches SSPADD it is loaded into SSPBUF 3 1 Receive First Address Byte 9 ACK 1 3 4 5 6 7 8 Software updates SSPADD and releases SCL 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSPBUF SCL is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0
2012 Microchip Technology Inc.
DS41639A-page 232 Preliminary D/A R/W ACKSTAT CKP UA BF SSPIF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSPADD must be updated SSPBUF loaded with received address 2 8 9 1 SCL S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSPADD is updated, UA is cleared and SCL is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the m
PIC16(L)F1454/5/9 22.5.6 22.5.6.2 CLOCK STRETCHING Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching.
PIC16(L)F1454/5/9 22.5.8 In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices.
PIC16(L)F1454/5/9 22.6 I2C MASTER MODE 22.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. The master device generates all of the serial clock pulses and the Start and Stop conditions.
PIC16(L)F1454/5/9 22.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and begins counting.
PIC16(L)F1454/5/9 22.6.4 I2C MASTER MODE START ister will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. CONDITION TIMING To initiate a Start condition (Figure 22-26), the user sets the Start Enable bit, SEN bit of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and starts its count.
PIC16(L)F1454/5/9 22.6.5 I2C MASTER MODE REPEATED SSPCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPSTAT register will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out.
PIC16(L)F1454/5/9 22.6.6 I2C MASTER MODE TRANSMISSION 22.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted.
DS41639A-page 240 S Preliminary R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written by software Cleared by software service routine from SSP interrupt 2 D6 Tran
PIC16(L)F1454/5/9 22.6.7 I2C MASTER MODE RECEPTION 22.6.7.4 Master mode reception (Figure 22-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSPCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR.
DS41639A-page 242 Preliminary RCEN ACKEN SSPOV BF (SSPSTAT<0>) SDA = 0, SCL = 1 while CPU responds to SSPIF SSPIF S 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK 2 3 5 6 7 8 D0 9 ACK 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSPIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDA = ACKDT = 0 Cleared in software Set SSPIF at end of receive 9 ACK is not s
PIC16(L)F1454/5/9 22.6.8 ACKNOWLEDGE SEQUENCE TIMING 22.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC16(L)F1454/5/9 22.6.10 SLEEP OPERATION 22.6.13 2 While in Sleep mode, the I C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 22.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 22.6.
PIC16(L)F1454/5/9 22.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 22-33). SCL is sampled low before SDA is asserted low (Figure 22-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 22-35).
PIC16(L)F1454/5/9 FIGURE 22-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC16(L)F1454/5/9 22.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 22-36). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC16(L)F1454/5/9 22.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 22-34).
PIC16(L)F1454/5/9 TABLE 22-3: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INTE IOCIE TMR0IF INTF IOCIF 96 Bit 7 Bit 6 Bit 5 Bit 4 GIE PEIE TMR0IE (2) PIE1 TMR1GIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 97 PIE2 OSFIE C2IE C1IE — BCL1IE USBIE ACTIE — 98 PIR1 TMR1GIF ADIF(2) RCIF TXIF SSP1IF — TMR2IF TMR1IF 99 PIR2 OSFIF C2IF C1IF — BCL1IF USBIF ACTIF — 100 — — TRISA5 TRISA4 —(1) — —(1)
PIC16(L)F1454/5/9 22.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPADD register (Register 22-6). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. clock line.
PIC16(L)F1454/5/9 22.
PIC16(L)F1454/5/9 REGISTER 22-1: bit 0 SSPSTAT: SSP STATUS REGISTER (CONTINUED) BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty DS41639A-page 252 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 REGISTER 22-2: SSPCON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode:
PIC16(L)F1454/5/9 REGISTER 22-3: SSPCON2: SSP CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit
PIC16(L)F1454/5/9 REGISTER 22-4: SSPCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is
PIC16(L)F1454/5/9 REGISTER 22-5: R/W-1/1 SSPMSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD to detect I2C address match 0 = The received address b
PIC16(L)F1454/5/9 23.
PIC16(L)F1454/5/9 FIGURE 23-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC SPBRGH SPBRGL x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 (8) ••• 7 1 LSb 0 START RX9 ÷n BRG16 Multiplier Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA)
PIC16(L)F1454/5/9 23.1 EUSART Asynchronous Mode 23.1.1.2 The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16(L)F1454/5/9 23.1.1.5 TSR Status 23.1.1.7 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 23.1.1.6 1. 2. 3.
PIC16(L)F1454/5/9 TABLE 23-1: Name BAUDCON INTCON SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 269 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 96 RCIE TXIE SSP1IE — TMR2IE TMR1IE 97 TMR1GIE PIE1 TMR1GIF PIR1 RCSTA SPEN (2) ADIE ADIF (2) RX9 RCIF TXIF SSP1IF — TMR2IF TMR1IF 99 SREN CREN ADDEN FERR OERR RX9D 268* SPBRGL SPBRGH (1)
PIC16(L)F1454/5/9 23.1.2 EUSART ASYNCHRONOUS RECEIVER 23.1.2.2 The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 23-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16(L)F1454/5/9 23.1.2.4 Receive Framing Error 23.1.2.7 Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
PIC16(L)F1454/5/9 23.1.2.8 Asynchronous Reception Set-up: 23.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 23.4 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register.
PIC16(L)F1454/5/9 TABLE 23-2: Name BAUDCON INTCON SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 269 GIE PEIE TMR1GIE PIE1 TMR1GIF PIR1 TMR0IE INTE IOCIE TMR0IF INTF IOCIF 96 (2) RCIE TXIE SSP1IE — TMR2IE TMR1IE 97 (2) RCIF TXIF SSP1IF — TMR2IF TMR1IF ADIE ADIF RCREG RCSTA EUSART Receive Data Register SPEN RX9 SREN SPBRGL CREN ADDEN FERR
PIC16(L)F1454/5/9 23.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output.
PIC16(L)F1454/5/9 23.
PIC16(L)F1454/5/9 RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) REGISTER 23-2: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/C
PIC16(L)F1454/5/9 REGISTER 23-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto
PIC16(L)F1454/5/9 23.4 EUSART Baud Rate Generator (BRG) EXAMPLE 23-1: The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode.
PIC16(L)F1454/5/9 TABLE 23-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: Name BAUDCON SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — W
PIC16(L)F1454/5/9 TABLE 23-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate % Error FOSC = 11.0592 MHz SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.
PIC16(L)F1454/5/9 TABLE 23-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 4.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 3.6864 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 1.000 MHz SPBRG Actual % value Rate Error (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.
PIC16(L)F1454/5/9 TABLE 23-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 20.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 18.432 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 16.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 11.0592 MHz SPBRG Actual % value Rate Error (decimal) 300 1200 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200.1 0.00 0.01 13332 3332 300.0 1200 0.
PIC16(L)F1454/5/9 23.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge.
PIC16(L)F1454/5/9 23.4.2 AUTO-BAUD OVERFLOW 23.4.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RX pin.
PIC16(L)F1454/5/9 FIGURE 23-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set.
PIC16(L)F1454/5/9 23.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted.
PIC16(L)F1454/5/9 23.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16(L)F1454/5/9 FIGURE 23-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
PIC16(L)F1454/5/9 23.5.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16(L)F1454/5/9 FIGURE 23-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16(L)F1454/5/9 23.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
PIC16(L)F1454/5/9 23.5.2.3 EUSART Synchronous Slave Reception 23.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 23.5.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16(L)F1454/5/9 23.6 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 23.6.
PIC16(L)F1454/5/9 NOTES: DS41639A-page 286 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 24.0 PULSE WIDTH MODULATION (PWM) MODULE For a step-by-step procedure on how to set up this module for PWM operation, refer to Section 24.1.9 “Setup for PWM Operation using PWMx Pins”.
PIC16(L)F1454/5/9 24.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. Note: 24.1.1 Clearing the PWMxOE bit will relinquish control of the PWMx pin. FUNDAMENTAL OPERATION The PWM module produces a 10-bit resolution output. Timer2 and PR2 set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle.
PIC16(L)F1454/5/9 24.1.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 24-4.
PIC16(L)F1454/5/9 24.1.9 SETUP FOR PWM OPERATION USING PWMx PINS The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. 2. 3. 4. 5. 6. 7. 8. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the PR2 register with the PWM period value. Clear the PWMxDCH register and bits <7:6> of the PWMxDCL register. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register.
PIC16(L)F1454/5/9 24.
PIC16(L)F1454/5/9 REGISTER 24-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWMxDCH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle.
PIC16(L)F1454/5/9 25.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE (PIC16(L)F1455/9 ONLY) The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band delay from a selection of input sources.
2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 FIGURE 25-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN) cwg_clock PWM1 CWGxA Rising Edge Deadband Rising Edge Deadband Falling Edge Deadband Rising Edge D Falling Edge Deadband CWGxB 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 25.1 Fundamental Operation 25.4.2 The CWG generates a two output complementary waveform from one of four selectable input sources. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output thereby creating an immediate time delay where neither output is driven. This is referred to as dead time and is covered in Section 25.5 “Dead-Band Control”.
PIC16(L)F1454/5/9 25.7 Falling Edge Dead Band The falling edge dead band delays the turn-on of the CWGxB output from when the CWGxA output is turned off. The falling edge dead-band time starts when the falling edge of the input source goes true. When this happens, the CWGxA output is immediately turned off and the falling edge dead-band delay time starts. When the falling edge dead-band delay time is reached, the CWGxB output is turned on.
2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 EQUATION 25-1: DEAD-BAND UNCERTAINTY 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock Example: Fcwg_clock = 16 MHz Therefore: 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock 1 = ------------------16 MHz = 625ns 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 25.9 Auto-Shutdown Control 25.10 Operation During Sleep Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for the safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. 25.9.1 SHUTDOWN The shutdown state can be entered by either of the following two methods: • Software generated • External Input 25.9.1.
PIC16(L)F1454/5/9 25.11 Configuring the CWG 25.11.1 The following steps illustrate how to properly configure the CWG to ensure a synchronous start: The levels driven to the output pins, while the shutdown input is true, are controlled by the GxASDLA and GxASDLB bits of the CWGxCON1 register (Register 25-2). GxASDLA controls the CWG1A override level and GxASDLB controls the CWG1B override level. The control bit logic level corresponds to the output logic drive level while in the shutdown state.
2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 25.
PIC16(L)F1454/5/9 REGISTER 25-2: R/W-x/u CWGxCON1: CWG CONTROL REGISTER 1 R/W-x/u GxASDLB<1:0> R/W-x/u R/W-x/u U-0 GxASDLA<1:0> — U-0 R/W-0/0 R/W-0/0 GxIS<1:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 GxASDLB<1:0>: CWGx Shutdown State for CWGxB When an auto-shutdo
PIC16(L)F1454/5/9 REGISTER 25-3: CWGxCON2: CWG CONTROL REGISTER 2 R/W-0/0 R/W-0/0 GxASE GxARSEN U-0 — U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — GxASDC2 GxASDC1 GxASDFLT — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 GxASE: Auto-Shutdown Event Status bit 1 = An auto-shutdow
PIC16(L)F1454/5/9 REGISTER 25-4: U-0 CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING DEAD-BAND COUNT REGISTER U-0 — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CWGxDBR<5:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CWGx
PIC16(L)F1454/5/9 TABLE 25-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH CWG(2) Bit 7 ANSELA CWGxCON0 CWGxCON1 CWGxCON2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Registe r on Page — — — ANSA4 — — — — 133 GxEN GxOEB GxOEA GxPOLB GxPOLA — — G1CS0 303 — — GxASDC2 GxASDC1 GxASDLB<1:0> GxASE GxARSEN GxASDLA<1:0> — — GxIS<1:0> GxASDFLT 304 — 305 — CWGxDBF<5:0> 306 — — CWGxDBR<5:0> 306 LATA — — LATA5 LATA4 — — — — 133 TRISA — — TRISA5 TRISA4 —(1) — —(1
PIC16(L)F1454/5/9 NOTES: DS41639A-page 308 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 26.0 UNIVERSAL SERIAL BUS (USB) 26.1 This device contains a full-speed and low-speed compatible USB Serial Interface Engine (SIE) that allows fast communication between any USB host and the microcontroller. The SIE can be interfaced directly to the USB by utilizing the internal transceiver. Some special hardware features have been included to improve performance.
PIC16(L)F1454/5/9 26.2 USB Status and Control The operation of the USB module is configured and managed through three control registers. In addition, a total of 14 registers are used to manage the actual USB transactions. The registers are: • • • • • • USB Control register (UCON) USB Configuration register (UCFG) USB Transfer Status register (USTAT) USB Device Address register (UADDR) Frame Number registers (UFRMH:UFRML) Endpoint Enable registers 0 through 7 (UEPn) 26.2.
PIC16(L)F1454/5/9 26.2.2.1 Internal Transceiver 26.2.2.3 Ping-Pong Buffer Configuration The USB peripheral has a full-speed and low-speed USB 2.0 capable transceiver internally built-in and connected to the SIE. The internal transceiver is enabled when the USBEN bit of the USBCON register is set. Full-speed operation is selected by setting the FSEN bit of the UCFG register. The usage of ping-pong buffers is configured using the PPB bits of the UCFG register. Refer to Section 26.4.
PIC16(L)F1454/5/9 26.2.3 USB STATUS (USTAT) REGISTER The USB Status register (Register 26-3) reports the transaction status within the SIE. When the SIE issues a USB transaction complete interrupt (TRNIF bit), USTAT should be read to determine the status of the transfer. USTAT contains the transfer endpoint number, direction and Ping-Pong Buffer Pointer value (if used). Note: The data in the USB Status register is valid two SIE clocks after the TRNIF bit is asserted.
PIC16(L)F1454/5/9 26.3 USB RAM 26.4 USB data moves between the microcontroller core and the SIE through the dual-port USB RAM. This is a special dual access memory that is mapped into a normal data memory space (Figure 26-3). The dual-port general purpose memory space is used specifically for endpoint buffer control. Depending on the type of buffering being used, all but 8 bytes of Bank 0 may also be available for use as USB buffer space.
PIC16(L)F1454/5/9 FIGURE 26-4: 2000h 2001h 2002h 2003h EXAMPLE OF A BUFFER DESCRIPTOR BD0STAT BD0CNT BD0ADRL BD0ADRH (xxh) (40h) (80h) (20h) Size of Block Starting Address The BDnSTAT byte of the BDT should always be the last byte updated when preparing to arm an endpoint. The SIE will clear the UOWN bit when a transaction has completed. 2080h Buffer USB Data 20BFh Note: 26.4.1 Memory regions not to scale.
PIC16(L)F1454/5/9 TABLE 26-1: OUT Packet from Host EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION BDnSTAT Settings Device Response after Receiving Packet DTSEN DTS Handshake UOWN TRNIF BDnSTAT and USTAT Status DATA0 1 0 ACK 0 1 Updated DATA1 1 0 ACK 1 0 Not Updated DATA0 1 1 ACK 1 0 Not Updated DATA1 1 1 ACK 0 1 Updated Either 0 x ACK 0 1 Updated Either, with error x x NAK 1 0 Not Updated Legend: x = don’t care 26.4.1.
PIC16(L)F1454/5/9 FIGURE 26-5: BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES PPB<1:0> = 00 No Ping-Pong Buffers 2000h PPB<1:0> = 01 Ping-Pong Buffer on EP0 OUT PPB<1:0> = 10 Ping-Pong Buffers on all EPs EP0 OUT 2000h Descriptor 2000h EP0 OUT Even Descriptor EP0 IN Descriptor EP0 OUT Odd Descriptor EP0 IN Descriptor EP0 OUT Odd Descriptor EP0 IN Descriptor EP1 OUT Descriptor EP0 IN Even Descriptor EP1 IN Descriptor EP1 OUT Descriptor EP1 OUT Even Descriptor EP0 IN Odd Descriptor EP1 IN
PIC16(L)F1454/5/9 TABLE 26-3: Name SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BDnSTAT(1) UOWN DTS(4) PID3(2) PID2(2) PID1(2) DTSEN(3) PID0(2) BSTALL(3) BC9 BC8 BDnCNT(1) Byte Count BDnADRL(1) Buffer Address Low BDnADRH(1) Buffer Address High Note 1: 2: 3: 4: For buffer descriptor registers, n may have a value of 0 to 31. For the sake of brevity, all 32 registers are shown as one generic prototype.
PIC16(L)F1454/5/9 26.5 USB Interrupts level and interrupts are enabled through the UIE register, while flags are maintained through the UIF register. USB error conditions are considered the second level and interrupts are enabled through the UEIE register, while flags are maintained through the UEIF register. Any USB interrupt condition will trigger the USB Error Interrupt Flag, the UERRIF bit of the UIF register. The USB module can generate multiple interrupt conditions.
PIC16(L)F1454/5/9 26.5.1 USB INTERRUPT STATUS (UIR) REGISTER 26.5.2 The USB Interrupt Status register (Register 26-7) contains the flag bits for each of the USB Status interrupt sources. Each of these sources has a corresponding interrupt enable bit in the UIE register. All of the USB status flags are ORed together to generate the USBIF interrupt flag for the microcontroller's interrupt funnel. Once an interrupt bit has been set by the SIE, it must be cleared by software.
PIC16(L)F1454/5/9 26.6 USB Power Modes The USB peripheral often has different power requirements and configurations depending on the application. The most common cases are presented here: In order to meet compliance specifications, the USB module (and the D+ or D- internal pull-ups) should not be enabled until the host actively drives VBUS high. The application should never source any current onto the 5V VBUS pin of the USB cable.
PIC16(L)F1454/5/9 26.6.4 USB TRANSCEIVER CURRENT CONSUMPTION The USB transceiver consumes a variable amount of current, depending on following factors: • • • • Impedance of USB cable Length of cable VUSB3V3 supply voltage Data patterns across cable Note: Longer cables have larger capacitance and consume more total energy when switching output states. Data patterns consist of “IN” and “OUT” traffic.
PIC16(L)F1454/5/9 EQUATION 26-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION IXCVR = Legend: (60 mA • VUSB3V3 • PZERO • PIN • LCABLE) + IPULLUP (3.3V • 5m) VUSB3V3: Voltage on the VUSB3V3 pin in volts. For F devices, VUSB3V3 = 3.3V supplied from the internal regulator, VDD 3.6V. For LF devices, VUSB3V3 is supplied by VDD 3.0 VDD 3.6. PZERO: Percentage of the IN traffic bits sent by the PIC® device that are a value of ‘0’. PIN: Percentage of total bus bandwidth that is used for IN traffic.
PIC16(L)F1454/5/9 26.7 Oscillator The USB module has specific clock requirements. For full-speed operation, the clock source must be 48 MHz. Even so, the microcontroller core and other peripherals are not required to run at that clock speed. Available clocking options are described in detail in Section 5.4 “USB Operation”. 26.
PIC16(L)F1454/5/9 26.10 USB Operation Overview 26.10.2 This section presents some of the basic USB concepts and useful information necessary to design a USB device. Although a lot of information is provided in this section, refer to the USB 2.0 specification for more details, as needed. Information communicated on the bus is grouped into 1 ms time slots, referred to as frames. Each frame can contain many transactions to various devices and endpoints.
PIC16(L)F1454/5/9 26.10.4 POWER 26.10.6 Power is available from the USB. The USB specification defines the bus power requirements. Devices may either be self-powered or bus powered. Self-powered devices draw power from an external source, while bus powered devices use power supplied from the bus. The USB specification limits the power taken from the bus. Refer to USB Specification 2.0, 7.2.3 for power limits information.
PIC16(L)F1454/5/9 26.
PIC16(L)F1454/5/9 REGISTER 26-2: R/W-0 UCFG: USB CONFIGURATION REGISTER R/W-0 UTEYE Reserved U-0 — R/W-0 UPUEN (1) R/W-0 Reserved R/W-0 R/W-0 (1) FSEN R/W-0 PPB<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test enabled 0 = Eye pattern test disabled x = Bit is unknown bit 5 Reserved: Read as ‘0’.
PIC16(L)F1454/5/9 REGISTER 26-3: U-0 USTAT: USB STATUS REGISTER R-x — R-x R-x R-x ENDP<3:0> R-x R-x U-0 DIR PPBI(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 ENDP<2:0>: Encoded Number of Last Endpoint Activity bits (represents the number of the BDT updated by the last USB transfer) 1111 = Endpoint 15 1110 = Endpoint 14 • • • 0001 = Endpoin
PIC16(L)F1454/5/9 REGISTER 26-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP7) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake enabled 0 = Endpoint handshake dis
PIC16(L)F1454/5/9 REGISTER 26-5: R/W-x UOWN(1) BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD31STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE) R/W-x U-0 U-0 (2) (3) (3) DTS — — R/W-x R/W-x R/W-x R/W-x DTSEN BSTALL BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit(1) 1 = Refer to Register 26-6.
PIC16(L)F1454/5/9 REGISTER 26-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD31STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE MCU) R/W-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x UOWN — PID3 PID2 PID1 PID0 BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit 1 = The SIE owns the BD and its corresponding buffer 0 = Ref
PIC16(L)F1454/5/9 REGISTER 26-7: U-0 UIR: USB INTERRUPT STATUS REGISTER R/W-0 — SOFIF R/W-0 STALLIF R/W-0 IDLEIF R/W-0 (1) TRNIF (2) R/W-0 ACTVIF (3) R-0 UERRIF R/W-0 (4) URSTIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOFIF: Start-of-Frame Token Interrupt bit 1 = A Start-of-Frame token received by the SIE 0 = No Start-o
PIC16(L)F1454/5/9 REGISTER 26-8: UIE: USB INTERRUPT ENABLE REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 SOFIE: Start-of-Frame Token Interrupt Enable bit 1 = Start-of-Frame token interrupt enabled 0 = Start-of-Frame token interrupt disable
PIC16(L)F1454/5/9 REGISTER 26-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER R/C-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BTSEF: Bit Stuff Error Flag bit 1 = A bit stuff error has been detected 0 = No bit stuff error bit 6-5 Unimplemented: Read as ‘0’ bit 4 BTOEF: Bu
PIC16(L)F1454/5/9 REGISTER 26-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Bit stuff error interrupt enabled 0 = Bit stuff error interrupt disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 BTOEE
PIC16(L)F1454/5/9 TABLE 26-4: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on Page: INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 96 100 PIR2 OSFIF C2IF C1IF — BCL1IF USBIF ACTIF — PIE2 OSFIE C2IE C1IE — BCL1IE USBIE ACTIE — 98 UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 326 UCFG UTEYE Reserved — UPUEN Reserved FSEN DIR PPBI — 328 ADDR2 ADDR1 ADDR0 312 USTAT — UADDR
PIC16(L)F1454/5/9 27.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) 27.3 ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS Connection to a target device is typically done through an ICSP header.
PIC16(L)F1454/5/9 FIGURE 27-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins. For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry.
PIC16(L)F1454/5/9 28.0 INSTRUCTION SET SUMMARY 28.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC16(L)F1454/5/9 FIGURE 28-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (lite
PIC16(L)F1454/5/9 TABLE 28-3: PIC16(L)F1454/5/9 ENHANCED INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shi
PIC16(L)F1454/5/9 TABLE 28-3: PIC16(L)F1454/5/9 ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTI
PIC16(L)F1454/5/9 28.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND.
PIC16(L)F1454/5/9 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC16(L)F1454/5/9 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>.
PIC16(L)F1454/5/9 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F1454/5/9 LSLF Logical Left Shift MOVF f {,d} Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W.
PIC16(L)F1454/5/9 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] MOVLP Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) • Unchanged Status Affected: Syntax: [ label
PIC16(L)F1454/5/9 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged None Mode Syntax mm Prei
PIC16(L)F1454/5/9 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] None RETFIE RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16(L)F1454/5/9 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F1454/5/9 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: SWAPF f,d (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16(L)F1454/5/9 29.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16LF1454/5/9 ..................................................................... -0.
PIC16(L)F1454/5/9 PIC16F1454/5/9 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 29-1: VDD (V) 5.5 2.7 2.3 10 0 20 40 48 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 29-1 for each Oscillator mode’s supported frequencies. PIC16LF1454/5/9 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 29-2: 3.6 2.7 1.
PIC16(L)F1454/5/9 29.1 DC Characteristics: PIC16(L)F1454/5/9-I/E (Industrial, Extended) PIC16LF1454/5/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1454/5/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym. VDD Characteristic VDR VPOR* VPORR* Units PIC16LF1454/5/9 1.8 2.
PIC16(L)F1454/5/9 FIGURE 29-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: DS41639A-page 356 TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 29.2 DC Characteristics: PIC16(L)F1454/5/9-I/E (Industrial, Extended) PIC16LF1454/5/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1454/5/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max. Units — 2 — A 1.
PIC16(L)F1454/5/9 29.2 DC Characteristics: PIC16(L)F1454/5/9-I/E (Industrial, Extended) (Continued) PIC16LF1454/5/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1454/5/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max.
PIC16(L)F1454/5/9 29.2 DC Characteristics: PIC16(L)F1454/5/9-I/E (Industrial, Extended) (Continued) PIC16LF1454/5/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1454/5/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Typ† Max.
PIC16(L)F1454/5/9 29.3 DC Characteristics: PIC16(L)F1454/5/9-I/E (Power-Down) PIC16LF1454/5/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1454/5/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Power-down Current D022 D022 D022A D023 D023 D023A D023A Min.
PIC16(L)F1454/5/9 29.3 DC Characteristics: PIC16(L)F1454/5/9-I/E (Power-Down) (Continued) PIC16LF1454/5/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1454/5/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC16(L)F1454/5/9 29.4 DC Characteristics: PIC16(L)F1454/5/9-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D030 — — 0.8 V 4.5V VDD 5.5V — — 0.15 VDD V 1.8V VDD 4.5V with Schmitt Trigger buffer — — 0.2 VDD V 2.0V VDD 5.5V with SMBus — — 0.8 V 3.
PIC16(L)F1454/5/9 29.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA D112 VBE VDD for Bulk Erase 2.
PIC16(L)F1454/5/9 29.6 USB Module Specifications Operating Conditions-40°C TA +85°C (unless otherwise state) Param No. Sym Characteristic Min Typ Max Units Conditions D313 VUSB USB Voltage 3.0 — 3.6 V Voltage on VUSB3V3 pin must be in this range for proper USB operation D314 IIL Input Leakage on pin — — ±1 A VSS VPIN VDD pin athigh impedance D315 VILUSB Input Low Voltage for USB Buffer — — 0.8 V For VUSB3V3 range D316 VIHUSB Input High Voltage for USB Buffer 2.
PIC16(L)F1454/5/9 29.7 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 TH02 Sym. Characteristic Typ. Units JA Thermal Resistance Junction to Ambient 70 C/W 14-Pin PDIP package 95.3 C/W 14-Pin SOIC package 100 C/W 14-Pin TSSOP package 45.7 C/W 16-Pin QFN 4x4mm package 62.2 C/W 20-pin PDIP package 77.7 C/W 20-pin SOIC package 87.3 C/W 20-pin SSOP package 43.
PIC16(L)F1454/5/9 29.8 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16(L)F1454/5/9 29.9 AC Characteristics: PIC16(L)F1454/5/9-I/E FIGURE 29-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS12 OS02 OS11 OS03 CLKOUT (CLKOUT Mode) Note See Table 29-3 for timing information. 1: TABLE 29-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. Typ† Max. Units Conditions DC — 0.
PIC16(L)F1454/5/9 FIGURE 29-6: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 29-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS11 Sym. TosH2ckL Characteristic Min. Typ† Max.
PIC16(L)F1454/5/9 FIGURE 29-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 29-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’.
PIC16(L)F1454/5/9 TABLE 29-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 10 16 27 ms VDD = 3.
PIC16(L)F1454/5/9 TABLE 29-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler — — ns — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns 0.
PIC16(L)F1454/5/9 TABLE 29-7: PIC16(L)F1454/5/9 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym. Characteristic AD130* TAD AD131 TCNV AD132* TACQ Min. Typ† Max. Units Conditions A/D Clock Period 1.0 — 9.0 s TOSC-based A/D Internal FRC Oscillator Period 1.0 1.6 6.
PIC16(L)F1454/5/9 FIGURE 29-11: PIC16(L)F1454/5/9 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK 9 A/D Data 8 7 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample AD132 Sampling Stopped Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 TABLE 29-8: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param No. Sym. Characteristics CM01 VIOFF Input Offset Voltage CM02 VICM Min. Typ. Max. Units Comments — ±7.
PIC16(L)F1454/5/9 FIGURE 29-12: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 29-4 for load conditions. TABLE 29-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic Min. Max. Units US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V — 80 ns 1.8-5.
PIC16(L)F1454/5/9 FIGURE 29-14: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 29-4 for load conditions.
PIC16(L)F1454/5/9 FIGURE 29-16: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 29-4 for load conditions.
PIC16(L)F1454/5/9 TABLE 29-12: SPI MODE REQUIREMENTS Param No. Symbol Characteristic SP70* TSSL2SCH, SS to SCK or SCK input TSSL2SCL Min. Typ† Max. Units Conditions TCY — — ns SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns 100 — — ns 100 — — ns 3.0-5.5V — 10 25 ns 1.8-5.
PIC16(L)F1454/5/9 FIGURE 29-18: I2C™ BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 29-4 for load conditions. TABLE 29-13: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. Symbol SP90* TSU:STA SP91* THD:STA SP92* TSU:STO SP93 Characteristic Typ Max.
PIC16(L)F1454/5/9 TABLE 29-14: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time 1.
PIC16(L)F1454/5/9 NOTES: 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 DS41639A-page 382 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 30.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 NOTES: DS41639A-page 384 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 31.0 DEVELOPMENT SUPPORT 31.
PIC16(L)F1454/5/9 31.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 31.
PIC16(L)F1454/5/9 31.7 MPLAB SIM Software Simulator 31.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16(L)F1454/5/9 31.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 31.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16(L)F1454/5/9 32.0 PACKAGING INFORMATION 32.1 Package Marking Information 14-Lead PDIP (300 mil) Example PIC16F1454 -E/P e3 1220123 14-Lead SOIC (3.90 mm) Example PIC16F1455 -E/SL e3 1220123 Legend: XX...X Y YY WW NNN e3 * Note: * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free.
PIC16(L)F1454/5/9 14-Lead TSSOP (4.4 mm) Example XXXXXXXX YYWW NNN F1454EST 1220 123 16-Lead QFN (4x4x0.9 mm) Example PIN 1 PIN 1 20-Lead PDIP (300 mil) Example PIC16F1459 -E/P e3 1220123 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN DS41639A-page 390 PIC16 F1455 E/ML e3 220123 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 20-Lead SOIC (7.50 mm) Example PIC16F1459 -E/SO e3 1220123 20-Lead SSOP (5.30 mm) Example PIC16F1459 -E/SS e3 1220123 Example 20-Lead QFN (4x4x0.9 mm) PIN 1 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 32.2 Package Details The following sections give the technical details of the packages.
PIC16(L)F1454/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41639A-page 394 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41639A-page 396 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 ! " # $ % & ' ( ( )* "# 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 D2 D EXPOSED PAD e E2 E 2 2 1 1 b TOP VIEW K N N NOTE 1 L BOTTOM VIEW A3 A A1 6 % & 9 & % 7!&( $ 99 - - 7 7 7: ; ? % : 8 % > % " $$ 0 + % % 4 , : = "% - -# -
PIC16(L)F1454/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 + 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 eB e b 6 % & 9 & % 7!&( $ 7+8- 7 7 % ; % % 7: 1 + < < 0 , 0 1 % % 0 < < - , , , 0 " " 4 ! " % 4 ! " = "%
PIC16(L)F1454/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41639A-page 402 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 + ,-.
PIC16(L)F1454/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41639A-page 404 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 + " # $ % & ' ( ( )* "# 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 6 % & 9 & % 7!&( $ 99 - - 7 7 7: ; % : 8 % > % " $$ 0 + % % 4 0 1 + , : = "% -
PIC16(L)F1454/5/9 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 DS41639A-page 406 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (06/2012) Initial release. 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 NOTES: DS41639A-page 408 Preliminary 2012 Microchip Technology Inc.
PIC16(L)F1454/5/9 INDEX A A/D Specifications.................................................... 371, 372 Absolute Maximum Ratings .............................................. 353 AC Characteristics Industrial and Extended ............................................ 367 Load Conditions ........................................................ 366 ACKSTAT ......................................................................... 238 ACKSTAT Status Flag ......................................................
PIC16(L)F1454/5/9 Code Examples A/D Conversion ......................................................... 159 Initializing PORTA............................................. 129, 131 Writing to Flash Program Memory ............................ 121 Comparator Associated Registers ................................................ 181 Operation .................................................................. 173 Comparator Module ..........................................................
PIC16(L)F1454/5/9 Start Condition Timing .............................. 236, 237 Transmission .................................................... 238 Multi-Master Communication, Bus Collision and Arbitration .................................................. 243 Multi-Master Mode .................................................... 243 Read/Write Bit Information (R/W Bit) ........................ 219 Slave Mode Transmission .................................................... 224 Sleep Operation ..........
PIC16(L)F1454/5/9 INTOSC ...................................................................... 57 LP................................................................................ 57 RC ............................................................................... 57 XT ............................................................................... 57 Oscillator Parameters........................................................ 367 Oscillator Specifications ...............................................
PIC16(L)F1454/5/9 IOCBF (Interrupt-on-Change PORTB Flag).............. 147 IOCBN (Interrupt-on-Change PORTB Negative Edge) ................................................. 147 IOCBP (Interrupt-on-Change PORTB Positive Edge)................................................... 146 LATA (Data Latch PORTA)....................................... 133 LATB (Data Latch PORTB)....................................... 137 LATC (Data Latch PORTC) ...................................... 141 OPTION_REG (OPTION) ...........
PIC16(L)F1454/5/9 Timers Timer1 T1CON.............................................................. 195 T1GCON ........................................................... 196 Timer2 T2CON.............................................................. 201 Timing Diagrams A/D Conversion ......................................................... 372 A/D Conversion (Sleep Mode) .................................. 373 Acknowledge Sequence ........................................... 242 Asynchronous Reception ......
PIC16(L)F1454/5/9 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16(L)F1454/5/9 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16(L)F1454/5/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.
