Datasheet
1998-2013 Microchip Technology Inc. DS40182D-page 95
PIC16CE62X
13.6 EEPROM Timing
FIGURE 13-10: BUS TIMING DATA
TABLE 13-7: AC CHARACTERISTICS
Parameter Symbol
STANDARD
MODE
Vcc = 4.5 - 5.5V
FAST MODE
Units Remarks
Min. Max. Min. Max.
Clock frequency F
CLK — 100 — 400 kHz
Clock high time T
HIGH 4000 — 600 — ns
Clock low time TLOW 4700 — 1300 — ns
SDA and SCL rise time TR — 1000 — 300 ns (Note 1)
SDA and SCL fall time T
F — 300 — 300 ns (Note 1)
START condition hold time THD:STA 4000 — 600 — ns After this period the first
clock pulse is generated
START condition setup time T
SU:STA 4700 — 600 — ns Only relevant for repeated
START condition
Data input hold time T
HD:DAT 0 — 0 — ns (Note 2)
Data input setup time TSU:DAT 250 — 100 — ns
STOP condition setup time T
SU:STO 4000 — 600 — ns
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time T
BUF 4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time from V
IH
minimum to VIL maximum
T
OF — 250 20 + 0.1
CB
250 ns (Note 1), CB 100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP — 50 — 50 ns (Note 3)
Write cycle time T
WR — 10 — 10 ms Byte or Page mode
Endurance
—
10M
1M
—10M
1M
—cycles
25°C, V
CC = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns)
of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike sup-
pression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on our website.
SCL
SDA
IN
SDA
OUT
T
HD:STA
TSU:STA
TF
THIGH
TR
TSU:STOTSU:DATTHD:DAT
TBUFTAA
THD:STA
TAA
TSP
TLOW