Datasheet

PIC16CE62X
DS40182D-page 62  1998-2013 Microchip Technology Inc.
FIGURE 10-17: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 10-18: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits
 BOREN CP1 CP0 PWRTE WDTE FOSC1 FOSC0
81h OPTION
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend:
_
= Unimplemented location, read as “0”, + = Reserved for future use
Note: Shaded cells are not used by the Watchdog Timer.
From TMR0 Clock Source
(Figure 7-6)
To TMR0 (Figure 7-6)
Postscaler
Watchdog
Timer
M
U
X
PSA
8 - to -1 MUX
PSA
WDT
Time-out
1
0
0
1
WDT
Enable Bit
PS<2:0>
•
•
Note: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
8
MUX