Datasheet

PIC16CE62X
DS40182D-page 54  1998-2013 Microchip Technology Inc.
10.4 Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOD)
10.4.1 POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in reset until
V
DD has reached a high enough level for proper opera-
tion. To take advantage of the POR, just tie the MCLR
pin through a resistor to VDD. This will eliminate exter-
nal RC components usually needed to create Power-on
Reset. A maximum rise time for VDD is required. See
electrical specifications for details.
The POR circuit does not produce an internal reset
when V
DD declines.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting”.
10.4.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates on an internal RC
oscillator. The chip is kept in reset as long as PWRT is
active. The PWRT delay allows the V
DD to rise to an
acceptable level. A configuration bit, PW
RTE, can
disable (if set) or enable (if cleared or programmed) the
Power-up Timer. The Power-up Timer should always be
enabled when Brown-out Reset is enabled.
The Power-Up Time delay will vary from chip-to-chip
and due to V
DD, temperature and process variation.
See DC parameters for details.
10.4.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on power-on reset or wake-up from
SLEEP.
10.4.4 BROWN-OUT RESET (BOD)
The PIC16CE62X members have on-chip Brown-out
Reset circuitry. A configuration bit, BOREN, can disable
(if clear/programmed) or enable (if set) the Brown-out
Reset circuitry. If V
DD falls below 4.0V (refer to BVDD
parameter D005) for greater than parameter (TBOR) in
Table 13-5, the brown-out situation will reset the chip. A
reset won’t occur if VDD falls below 4.0V for less than
parameter (TBOR).
On any reset (Power-on, Brown-out, Watch-dog, etc.)
the chip will remain in reset until V
DD rises above BVDD.
The Power-up Timer will then be invoked and will keep
the chip in reset an additional 72 ms.
If V
DD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above BVDD, the Power-Up Timer will execute a
72 ms reset. The Power-up Timer should always be
enabled when Brown-out Reset is enabled. Figure 10-7
shows typical Brown-out situations.
FIGURE 10-7: BROWN-OUT SITUATIONS
72 ms
BV
DD
V
DD
Internal
Reset
BVDD
V
DD
Internal
Reset
72 ms
<72 ms
72 ms
BV
DD
V
DD
Internal
Reset