Datasheet

PIC16CE62X
DS40182D-page 48  1998-2013 Microchip Technology Inc.
EXAMPLE 9-1: VOLTAGE REFERENCE
CONFIGURATION
9.2 Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 9-1) keep V
REF from approaching VSS or VDD.
The Voltage Reference is V
DD derived and therefore,
the V
REF output changes with fluctuations in VDD. The
absolute accuracy of the Voltage Reference can be
found in Table 13-2.
9.3 Operation During Sleep
When the device wakes up from sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
MOVLW 0x02 ; 4 Inputs Muxed
MOVWF CMCON ; to 2 comps.
BSF STATUS,RP0 ; go to Bank 1
MOVLW 0x07 ; RA3-RA0 are
MOVWF TRISA ; outputs
MOVLW 0xA6 ; enable V
REF
MOVWF VRCON ; low range
; set V
R<3:0>=6
BCF STATUS,RP0 ; go to Bank 0
CALL DELAY10 ; 10s delay
9.4 Effects of a Reset
A device reset disables the Voltage Reference by clear-
ing bit V
REN (VRCON<7>). This reset also disconnects
the reference from the RA2 pin by clearing bit V
ROE
(VRCON<6>) and selects the high voltage range by
clearing bit V
RR (VRCON<5>). The VREF value select
bits, VRCON<3:0>, are also cleared.
9.5 Connection Considerations
The Voltage Reference Module operates
independently of the comparator module. The output of
the reference generator may be connected to the RA2
pin if the TRISA<2> bit is set and the V
ROE bit,
VRCON<6>, is set. Enabling the Voltage Reference
output onto the RA2 pin with an input signal present will
increase current consumption. Connecting RA2 as a
digital output with V
REF enabled will also increase
current consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
V
REF. Figure 9-2 shows an example buffering
technique.
FIGURE 9-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
TABLE 9-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Legend: - = Unimplemented, read as "0"
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value On
POR / BOD
Value On
All Other
Resets
9Fh VRCON VREN VROE VRR
—VR3VR2VR1VR0000- 0000 000- 0000
1Fh CMCON
C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000
85h TRISA
— — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
VREF Output
+
–
•
•
VREF
Module
Voltage
Reference
Output
Impedance
R
(1)
RA2
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.