Datasheet

PIC16CE62X
DS40182D-page 18  1998-2013 Microchip Technology Inc.
4.2.2.4 PIE1 REGISTER
This register contains the individual enable bit for the
comparator interrupt.
REGISTER 4-4: PIE1 REGISTER (ADDRESS 8CH)
U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
—CMIE— — — — — — R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
-x = Unknown at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6: CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
bit 5-0: Unimplemented: Read as '0'
4.2.2.5 PIR1 REGISTER
This register contains the individual flag bit for the com-
parator interrupt.
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
REGISTER 4-5: PIR1 REGISTER (ADDRESS 0CH)
U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
—CMIF— — — — — — R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
-x = Unknown at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6: CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed
0 = Comparator input has not changed
bit 5-0: Unimplemented: Read as '0'