Datasheet

PIC16CE62X
DS40182D-page 14  1998-2013 Microchip Technology Inc.
4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The Special Function Registers
associated with the “core” functions are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16CE62X
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR Reset
Value on all
other
resets
(1)
Bank 0
00h INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx xxxx xxxx
01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS
IRP
(2)
RP1
(2)
RP0 TO PD ZDCC
0001 1xxx 000q quuu
04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA
— — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
07h Unimplemented — —
08h Unimplemented — —
09h Unimplemented — —
0Ah PCLATH
— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1
—CMIF— — — — — — -0-- ---- -0-- ----
0Dh-1Eh Unimplemented — —
1Fh CMCON C2OUT C1OUT
— — CIS CM2 CM1 CM0 00-- 0000 00-- 0000
Bank 1
80h INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx xxxx xxxx
81h OPTION RBPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS IRP RP1 RP0 TO
PD ZDCC0001 1xxx 000q quuu
84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA
— — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
87h Unimplemented — —
88h Unimplemented — —
89h Unimplemented — —
8Ah PCLATH
— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1
—CMIE— — — — — — -0-- ---- -0-- ----
8Dh Unimplemented — —
8Eh PCON
— — — — — —PORBOD ---- --0x ---- --uq
8Fh-9Eh Unimplemented — —
90h EEINTF
— — — — — EESCL EESDA EEVDD ---- -111 ---- -111
9Fh VRCON VREN VROE VRR
— VR3 VR2 VR1 VR0 000- 0000 000- 0000
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR
reset, Brown-out Reset and Watchdog Timer Reset during normal
operation.
Note 2: IRP & RPI bits are reserved; always maintain these bits clear.