Datasheet

PIC16CE62X
DS40182D-page 12  1998-2013 Microchip Technology Inc.
4.2 Data Memory Organization
The data memory (Figure 4-4 and Figure 4-5) is
partitioned into two Banks which contain the General
Purpose Registers and the Special Function Registers.
Bank 0 is selected when the RP0 bit is cleared. Bank 1
is selected when the RP0 bit (STATUS <5>) is set. The
Special Function Registers are located in the first 32
locations of each Bank. Register locations 20-7Fh
(Bank0) on the PIC16CE623/624 and 20-7Fh (Bank0)
and A0-BFh (Bank1) on the PIC16CE625 are General
Purpose Registers implemented as static RAM. Some
special purpose registers are mapped in Bank 1. In all
three microcontrollers, address space F0h-FFh
(Bank1) is mapped to 70-7Fh (Bank0) as common
RAM.
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file is organized as 96 x 8 in the
PIC16CE623/624 and 128 x 8 in the PIC16CE625.
Each is accessed either directly or indirectly through
the File Select Register FSR (Section 4.4).