PIC16CE62X OTP 8-Bit CMOS MCU with EEPROM Data Memory Devices included in this data sheet: Pin Diagrams • PIC16CE623 • PIC16CE624 • PIC16CE625 PDIP, SOIC, Windowed CERDIP Device Program Memory RAM Data Memory EEPROM Data Memory PIC16CE623 512x14 96x8 128x8 PIC16CE624 1Kx14 96x8 128x8 PIC16CE625 2Kx14 128x8 128x8 • • • • Interrupt capability 16 special function hardware registers 8-level deep hardware stack Direct, Indirect and Relative addressing modes •1 2 3 4 5 6 7 8 9 18 17 16 15 1
PIC16CE62X Table of Contents 1.0 General Description ............................................................................................................................................... 3 2.0 PIC16CE62X Device Varieties .............................................................................................................................. 5 3.0 Architectural Overview..............................................................................................................................
PIC16CE62X 1.0 GENERAL DESCRIPTION The PIC16CE62X are 18 and 20-Pin EPROM-based members of the versatile PIC® family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with EEPROM data memory. All PIC® microcontrollers employ an advanced RISC architecture. The PIC16CE62X family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources.
PIC16CE62X TABLE 1-1: PIC16CE62X FAMILY OF DEVICES PIC16CE623 Clock Memory Peripherals Features PIC16CE624 PIC16CE625 Maximum Frequency of Operation (MHz) 20 20 EPROM Program Memory (x14 words) 512 1K 20 2K Data Memory (bytes) 96 96 128 EEPROM Data Memory (bytes) 128 128 128 Timer Module(s) TMR0 TMR0 TMR0 Comparators(s) 2 2 2 Internal Reference Voltage Yes Yes Yes Interrupt Sources 4 4 4 I/O Pins 13 13 13 Voltage Range (Volts) 2.5-5.5 2.5-5.5 2.5-5.
PIC16CE62X 2.0 PIC16CE62X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in the PIC16CE62X Product Identification System section at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number. 2.
PIC16CE62X NOTES: DS40182D-page 6 1998-2013 Microchip Technology Inc.
PIC16CE62X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CE62X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CE62X uses a Harvard architecture in which program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory.
PIC16CE62X FIGURE 3-1: BLOCK DIAGRAM Device Program Memory PIC16CE623 PIC16CE624 PIC16CE625 512 x 14 1K x 14 2K x 14 Data Memory (RAM) 96 x 8 96 x 8 128 x 8 EEPROM DATA MEMORY 128 x 8 128 x 8 128 x 8 13 Program Counter Voltage Reference 8 Data Bus EPROM Program Memory Program Bus RAM File Registers 8 Level Stack (13-bit) 14 RAM Addr (1) 9 Comparator RA0/AN0 Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr RA1/AN1 + RA2/AN2/VREF RA3/AN3 + FSR reg STATUS reg TMR0 3 MUX Pow
PIC16CE62X TABLE 3-1: Name PIC16CE62X PINOUT DESCRIPTION DIP/ SOIC Pin # SSOP Pin # I/O/P Type Buffer Type Description OSC1/CLKIN 16 18 I OSC2/CLKOUT 15 17 O ST/CMOS Oscillator crystal input/external clock source input. — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
PIC16CE62X 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2.
PIC16CE62X 4.0 MEMORY ORGANIZATION 4.1 Program Memory Organization The PIC16CE62X has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 512 x 14 (0000h - 01FFh) for the PIC16CE623, 1K x 14 (0000h - 03FFh) for the PIC16CE624 and 2K x 14 (0000h - 07FFh) for the PIC16CE625 are physically implemented.
PIC16CE62X 4.2 Data Memory Organization The data memory (Figure 4-4 and Figure 4-5) is partitioned into two Banks which contain the General Purpose Registers and the Special Function Registers. Bank 0 is selected when the RP0 bit is cleared. Bank 1 is selected when the RP0 bit (STATUS <5>) is set. The Special Function Registers are located in the first 32 locations of each Bank.
PIC16CE62X FIGURE 4-4: DATA MEMORY MAP FOR THE PIC16CE623/624 File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB PCLATH INTCON PIR1 PCLATH INTCON PIE1 PCON EEINTF CMCON VRCON FIGURE 4-5: File Address File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh
PIC16CE62X 4.2.2 SPECIAL FUNCTION REGISTERS The special registers can be classified into two sets (core and peripheral). The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (Table 4-1).
PIC16CE62X 4.2.2.1 STATUS REGISTER It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any status bit. For other instructions, not affecting any status bits, see the “Instruction Set Summary”. The STATUS register, shown in Register 4-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.
PIC16CE62X 4.2.2.2 OPTION REGISTER Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0 and the weak pull-ups on PORTB.
PIC16CE62X 4.2.2.3 INTCON REGISTER Note: The INTCON register is a readable and writable register which contains the various enable and flag bits for all interrupt sources except the comparator module. See Section 4.2.2.4 and Section 4.2.2.5 for a description of the comparator enable and flag bits. REGISTER 4-3: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PIC16CE62X 4.2.2.4 PIE1 REGISTER This register contains the individual enable bit for the comparator interrupt.
PIC16CE62X 4.2.2.6 PCON REGISTER The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR reset, WDT reset or a Brown-out Reset. Note: BOD is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOD is cleared, indicating a brown-out has occurred. The BOD status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming BODEN bit in the configuration word).
PIC16CE62X 4.3 4.3.2 PCL and PCLATH The program counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-6 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
PIC16CE62X 4.4 Indirect Addressing, INDF and FSR Registers A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 4-1. The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. EXAMPLE 4-1: Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h.
PIC16CE62X NOTES: DS40182D-page 22 1998-2013 Microchip Technology Inc.
PIC16CE62X 5.0 I/O PORTS Note: The PIC16CE62X parts have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. 5.1 PORTA and TRISA Registers PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Port RA4 is multiplexed with the T0CKI clock input.
PIC16CE62X FIGURE 5-3: Data Bus BLOCK DIAGRAM OF RA3 PIN Comparator Mode = 110 D Q Comparator Output WR PORTA VDD Q CK Data Latch D VDD P Q RA3 Pin N WR TRISA CK Q VSS Analog Input Mode TRIS Latch Schmitt Trigger Input Buffer RD TRISA Q D EN RD PORTA To Comparator FIGURE 5-4: Data Bus BLOCK DIAGRAM OF RA4 PIN Comparator Mode = 110 D Q Comparator Output WR PORTA CK Q Data Latch D WR TRISA Q N CK RA4 Pin Q VSS TRIS Latch Schmitt Trigger Input Buffer RD TRISA Q D EN RD PORTA
PIC16CE62X TABLE 5-1: PORTA FUNCTIONS Name Bit # Buffer Type RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3 RA4/T0CKI bit0 bit1 bit2 bit3 bit4 ST ST ST ST ST Function Input/output or comparator input Input/output or comparator input Input/output or comparator input or VREF output Input/output or comparator input/output Input/output or external clock input for TMR0 or comparator output. Output is open drain type.
PIC16CE62X 5.2 PORTB and TRISB Registers PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. A '1' in the TRISB register puts the corresponding output driver in a high impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected pin(s). Reading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations.
PIC16CE62X TABLE 5-3: Name PORTB FUNCTIONS Bit # Buffer Type Function Input/output or external interrupt input. Internal software programmable RB0/INT bit0 TTL/ST weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up.
PIC16CE62X 5.3 I/O Programming Considerations 5.3.1 BI-DIRECTIONAL I/O PORTS EXAMPLE 5-2: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
PIC16CE62X 6.0 EEPROM PERIPHERAL OPERATION The PIC16CE623/624/625 each have 128 bytes of EEPROM data memory. The EEPROM data memory supports a bi-directional, 2-wire bus and data transmission protocol. These two-wires are serial data (SDA) and serial clock (SCL), and are mapped to bit1 and bit2, respectively, of the EEINTF register (SFR 90h). In addition, the power to the EEPROM can be controlled using bit0 (EEVDD) of the EEINTF register.
PIC16CE62X 6.1 Bus Characteristics In this section, the term “processor” refers to the portion of the PIC16CE62X that interfaces to the EEPROM through software manipulating the EEINTF register. The following bus protocol is to be used with the EEPROM data memory. • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH.
PIC16CE62X FIGURE 6-1: SCL (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (C) (D) (C) (A) SDA START CONDITION FIGURE 6-2: STOP CONDITION ADDRESS OR DATA ACKNOWLEDGE ALLOWED VALID TO CHANGE ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 SDA 3 4 5 6 7 8 9 1 Device Addressing After generating a START condition, the processor transmits a control byte consisting of a EEPROM address and a Read/Write bit that indicates what type of operation is to be performed.
PIC16CE62X 6.3 Write Operations 6.4 6.3.1 BYTE WRITE Since the EEPROM will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the processor, the EEPROM initiates the internally timed write cycle. ACK polling can be initiated immediately.
PIC16CE62X FIGURE 6-6: BUS ACTIVITY PROCESSOR SDA LINE PAGE WRITE S T A R T CONTROL BYTE A C K Read Operation Current Address Read The EEPROM contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1.
PIC16CE62X FIGURE 6-7: CURRENT ADDRESS READ BUS ACTIVITY PROCESSOR S T A R T SDA LINE S CONTROL BYTE S T O P DATAn P N O A C K BUS ACTIVITY A C K FIGURE 6-8: RANDOM READ S T BUS ACTIVITY A PROCESSOR R T CONTROL BYTE S T A R T WORD ADDRESS (n) S SDA LINE CONTROL BYTE S T O P DATAn P S A C K BUS ACTIVITY A C K N O A C K A C K FIGURE 6-9: SEQUENTIAL READ BUS ACTIVITY PROCESSOR A C K CONTROL BYTE A C K S T O P A C K SDA LINE BUS ACTIVITY P A C K DATAn DATAn + 1 DATAn +
PIC16CE62X 7.0 TIMER0 MODULE bit (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. The Timer0 module timer/counter has the following features: • • • • • • The prescaler is shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable.
PIC16CE62X FIGURE 7-3: PC (Program Counter) TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 Instruction Fetch TMR0 PC PC+1 MOVWF TMR0 MOVF TMR0,W T0 PC+2 PC+3 T0+1 Instruction Execute PC+4 MOVF TMR0,W MOVF TMR0,W PC+5 MOVF TMR0,W PC+6 MOVF TMR0,W NT0+1 NT0 Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1 FIGURE 7-4:
PIC16CE62X 7.2 Using Timer0 with External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 7.2.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output.
PIC16CE62X 7.3 Prescaler The PSA and PS<2:0> bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 7-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is mutually exclusive between the Timer0 module and the Watchdog Timer.
PIC16CE62X 7.3.1 SWITCHING PRESCALER ASSIGNMENT To change prescaler from the WDT to the TMR0 module, use the sequence shown in Example 7-2. This precaution must be taken even if the WDT is disabled. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 7-1) must be executed when changing the prescaler assignment from Timer0 to WDT.
PIC16CE62X NOTES: DS40182D-page 40 1998-2013 Microchip Technology Inc.
PIC16CE62X 8.0 COMPARATOR MODULE The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RA0 through RA3 pins. The on-chip voltage reference (Section 9.0) can also be an input to the comparators. REGISTER 8-1: R-0 C2OUT bit7 The CMCON register, shown in Register 8-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 8-1.
PIC16CE62X 8.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select the mode. Figure 8-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the comparator FIGURE 8-1: RA0/AN0 RA3/AN3 RA1/AN1 RA2/AN2 mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Table 13-1.
PIC16CE62X The code example in Example 8-1 depicts the steps required to configure the comparator module. RA3 and RA4 are configured as digital output. RA0 and RA1 are configured as the V- inputs and RA2 as the V+ input to both comparators.
PIC16CE62X 8.4 Comparator Response Time 8.5 Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs, otherwise the maximum delay of the comparators should be used (Table 13-1 ). Comparator Outputs The comparator outputs are read through the CMCON register.
PIC16CE62X 8.6 Comparator Interrupts wake-up the device from SLEEP mode when enabled. While the comparator is powered-up, higher sleep currents than shown in the power down current specification will occur. Each comparator that is operational will consume additional current as shown in the comparator specifications. To minimize power consumption while in SLEEP mode, turn off the comparators, CM<2:0> = 111, before entering sleep.
PIC16CE62X TABLE 8-1: Address REGISTERS ASSOCIATED WITH COMPARATOR MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR Value on All Other Resets 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — CMIF — — — — — — -0-- ---- -0-- ---- 8Ch PIE1 — CMIE — — — — — — -0-- ---
PIC16CE62X 9.0 VOLTAGE REFERENCE MODULE 9.1 The Voltage Reference can output 16 distinct voltage levels for each range. The Voltage Reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of VREF values and has a power-down function to conserve power when the reference is not being used. The VRCON register controls the operation of the reference as shown in Register 9-1. The block diagram is given in Figure 9-1.
PIC16CE62X EXAMPLE 9-1: MOVLW VOLTAGE REFERENCE CONFIGURATION 0x02 ; 4 Inputs Muxed MOVWF CMCON ; to 2 comps. BSF STATUS,RP0 ; go to Bank 1 MOVLW 0x07 ; RA3-RA0 are MOVWF TRISA ; outputs MOVLW 0xA6 ; enable VREF MOVWF VRCON ; low range BCF STATUS,RP0 ; go to Bank 0 CALL DELAY10 ; 10s delay 9.4 A device reset disables the Voltage Reference by clearing bit VREN (VRCON<7>).
PIC16CE62X 10.0 SPECIAL FEATURES OF THE CPU Special circuits to deal with the needs of real time applications are what sets a microcontroller apart from other processors. The PIC16CE62X family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16CE62X 10.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h – 3FFFh), which can be accessed only during programming.
PIC16CE62X 10.2 Oscillator Configurations 10.2.1 OSCILLATOR TYPES LP XT HS RC 10.2.2 Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR / CERAMIC RESONATORS Mode FIGURE 10-1: CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION) OSC1 C1 To Internal Logic SLEEP RF OSC2 RS C2 see Note Note: A series resistor may be required for AT strip cut crystals. OSC1 OSC2 455 kHz 2.0 MHz 4.
PIC16CE62X 10.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance or one with parallel resonance. Figure 10-3 shows implementation of a parallel resonant oscillator circuit.
PIC16CE62X 10.3 Reset The PIC16CE62X differentiates between various kinds of reset: a) b) c) d) e) f) Power-on reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT reset (normal operation) WDT wake-up (SLEEP) Brown-out Reset (BOD) state” on Power-on reset, MCLR reset, WDT reset and MCLR reset during SLEEP. They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation.
PIC16CE62X 10.4 10.4.1 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) and Brown-out Reset (BOD) The Power-Up Time delay will vary from chip-to-chip and due to VDD, temperature and process variation. See DC parameters for details. POWER-ON RESET (POR) The Oscillator Start-Up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. 10.4.
PIC16CE62X 10.4.5 TIME-OUT SEQUENCE 10.4.6 On power-up, the time-out sequence is as follows: First PWRT time-out is invoked after POR has expired, then OST is activated. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in RC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 10-8, Figure 10-9 and Figure 10-10 depict time-out sequences. The power control/status register, PCON (address 8Eh) has two bits.
PIC16CE62X TABLE 10-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR reset during normal operation 000h 000u uuuu ---- --uu MCLR reset during SLEEP 000h 0001 0uuu ---- --uu WDT reset 000h 0000 uuuu ---- --uu PC + 1 uuu0 0uuu ---- --uu 000h 000x xuuu ---- --u0 uuu1 0uuu ---- --uu Condition WDT Wake-up Brown-out Reset Interrupt Wake-up from SLEEP PC + 1 (1) Legend: u = unchanged, x = unk
PIC16CE62X FIGURE 10-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 10-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 1998-2013 Microchip Technology Inc.
PIC16CE62X FIGURE 10-11: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 10-13: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 VDD VDD VDD VDD R1 Q1 D MCLR R R2 R1 40k PIC16CE62X MCLR PIC16CE62X C Note 1: External power-on reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: < 40 k is recommended to make sure that voltage drop across R does not violate the device’s electrical specification.
PIC16CE62X 10.5 Interrupts The PIC16CE62X has 4 sources of interrupt: • • • • External interrupt RB0/INT TMR0 overflow interrupt PortB change interrupts (pins RB<7:4>) Comparator interrupt The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts.
PIC16CE62X 10.5.1 RB0/INT INTERRUPT 10.5.3 External interrupt on RB0/INT pin is edge triggered; either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re-enabling this interrupt.
PIC16CE62X 10.6 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (i.e. W register and STATUS register). This will have to be implemented in software. Example 10-1 stores and restores the STATUS and W registers. The user register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e.
PIC16CE62X FIGURE 10-17: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 7-6) 0 Watchdog Timer • 1 M U X Postscaler 8 8 - to -1 MUX PS<2:0> • To TMR0 (Figure 7-6) PSA WDT Enable Bit 1 0 MUX PSA WDT Time-out Note: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. FIGURE 10-18: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name 2007h Config.
PIC16CE62X 10.8 Power-Down Mode (SLEEP) The Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit in the STATUS register is cleared, the TO bit is set and the oscillator driver is turned off. The I/O ports maintain the status they had before SLEEP was executed (driving high, low, or hi-impedance).
PIC16CE62X 10.9 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: 10.10 Microchip does not recommend code protecting windowed devices. ID Locations Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify.
PIC16CE62X 11.0 INSTRUCTION SET SUMMARY Each PIC16CE62X instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CE62X instruction set summary in Table 11-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 11-1 shows the opcode field descriptions.
PIC16CE62X TABLE 11-2: Mnemonic, Operands PIC16CE62X INSTRUCTION SET Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W
PIC16CE62X 11.1 Instruction Descriptions ANDLW AND Literal with W Syntax: [ label ] ANDLW ADDLW Add Literal and W Syntax: [ label ] ADDLW Operands: 0 k 255 Operands: 0 k 255 Operation: (W) + k (W) Operation: (W) .AND. (k) (W) Status Affected: C, DC, Z Status Affected: Z Encoding: 11 k 111x kkkk kkkk Encoding: 11 k 1001 kkkk kkkk Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
PIC16CE62X BCF Bit Clear f BTFSC Bit Test, Skip if Clear Syntax: [ label ] BCF Syntax: [ label ] BTFSC f,b Operands: 0 f 127 0b7 Operands: 0 f 127 0b7 Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 01 f,b 00bb bfff ffff Description: Bit 'b' in register 'f' is cleared.
PIC16CE62X BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRF Operands: 0 f 127 0b<7 Operands: 0 f 127 Operation: Operation: skip if (f) = 1 00h (f) 1Z Status Affected: None Status Affected: Z Encoding: Description: 01 11bb bfff ffff If bit 'b' in register 'f' is '1' then the next instruction is skipped.
PIC16CE62X CLRWDT Clear Watchdog Timer DECF Decrement f Syntax: [ label ] CLRWDT Syntax: [ label ] DECF f,d Operands: None Operands: Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD 0 f 127 d [0,1] Operation: (f) - 1 (dest) Status Affected: Z Status Affected: Encoding: Description: Encoding: TO, PD 00 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
PIC16CE62X GOTO Unconditional Branch INCFSZ Increment f, Skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 k 2047 Operands: Operation: k PC<10:0> PCLATH<4:3> PC<12:11> 0 f 127 d [0,1] Operation: (f) + 1 (dest), skip if result = 0 None Status Affected: None Status Affected: Encoding: Description: GOTO k 10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>.
PIC16CE62X IORWF Inclusive OR W with f MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (W) .OR. (f) (dest) Operation: (f) (dest) Status Affected: Z Status Affected: Z Encoding: 00 IORWF f,d 0100 dfff ffff Description: Inclusive OR the W register with register 'f'. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
PIC16CE62X NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS PC, 1 GIE Status Affected: None Encoding: 00 NOP 0000 Description: No operation. Words: 1 Cycles: 1 Example 0xx0 0000 Encoding: RETFIE 00 0000 0000 1001 Description: Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC.
PIC16CE62X RETURN Return from Subroutine Syntax: [ label ] Operands: None Operation: TOS PC Status Affected: None Encoding: Description: 00 0000 0000 1000 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.
PIC16CE62X SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (f) - (W) dest) Status Affected: C, DC, Z Encoding: 00 SUBLW k Operands: 0 k 255 Operation: k - (W) W) Status Affected: C, DC, Z Encoding: Description: 11 110x kkkk kkkk The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.
PIC16CE62X SWAPF Swap Nibbles in f XORLW Exclusive OR Literal with W Syntax: [ label ] SWAPF f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 Operation: (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) Operation: (W) .XOR. k W) Status Affected: Z None Encoding: Status Affected: Words: Cycles: 11 1010 kkkk The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.
PIC16CE62X 12.
PIC16CE62X MPLIB is a librarian for pre-compiled code to be used with MPLINK. When a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. MPLIB manages the creation and modification of library files. MPLINK features include: • MPLINK works with MPASM and MPLAB-C17 and MPLAB-C18.
PIC16CE62X stand-alone mode the PRO MATE II can read, verify or program PIC devices. It can also set code-protect bits in this mode. 12.11 PICSTART Plus Entry Level Development System The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus supports all PIC devices with up to 40 pins.
PIC16CE62X and test the sample code. In addition, PICDEM-17 supports down-loading of programs to and executing out of external FLASH memory on board. The PICDEM-17 is also usable with the MPLAB-ICE or PICMASTER emulator, and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware. 12.17 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs.
1998-2013 Microchip Technology Inc.
PIC16CE62X NOTES: DS40182D-page 7-82 1998-2013 Microchip Technology Inc.
PIC16CE62X 13.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings † Ambient Temperature under bias .............................................................................................................. -40 to +125C Storage Temperature ................................................................................................................................ -65 to +150C Voltage on any pin with respect to VSS (except VDD and MCLR)........................................................-0.
PIC16CE62X FIGURE 13-1: PIC16CE62X VOLTAGE-FREQUENCY GRAPH, 0C TA +70C 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
PIC16CE62X FIGURE 13-3: PIC16LCE62X VOLTAGE-FREQUENCY GRAPH, -40C TA +125C 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. 1998-2013 Microchip Technology Inc.
PIC16CE62X 13.1 DC CHARACTERISTICS: PIC16CE62X-04 (Commercial, Industrial, Extended) PIC16CE62X-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature –40C TA +85C for industrial and 0C TA +70C for commercial and –40C TA +125C for extended DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units Conditions D001 VDD Supply Voltage 3.0 – 5.
PIC16CE62X 13.2 DC CHARACTERISTICS: PIC16LCE62X-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature –40C TA +85C for industrial and 0C TA +70C for commercial and –40C TA +125C for extended DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units Conditions D001 VDD Supply Voltage 2.5 – 5.5 V See Figure 13-1 through Figure 13-3 D002 VDR RAM Data Retention Voltage (Note 1) – 1.
PIC16CE62X 13.3 DC CHARACTERISTICS: DC CHARACTERISTICS Parm No.
PIC16CE62X TABLE 13-1: COMPARATOR SPECIFICATIONS Operating Conditions: VDD range as described in Table 12-1, -40C
PIC16CE62X 13.4 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16CE62X 13.5 Timing Diagrams and Specifications FIGURE 13-5: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 13-3: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter No. Sym Characteristic Min 1A Fosc External CLKIN Frequency (Note 1) DC — 4 MHz XT and RC osc mode, VDD=5.0V DC — 20 MHz HS osc mode DC — 200 kHz LP osc mode Oscillator Frequency (Note 1) DC — 4 MHz RC osc mode, VDD=5.0V 0.
PIC16CE62X FIGURE 13-6: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: All tests must be do with specified capacitance loads (Figure 13-4) 50 pF on I/O pins and CLKOUT TABLE 13-4: Parameter # CLKOUT AND I/O TIMING REQUIREMENTS Sym Characteristic 10* TosH2ckL OSC1 to CLKOUT (1) 11* TosH2ckH 12* TckR CLKOUT rise time 13* TckF CLKOUT fall time (1) 14* TckL2ioV CLKOUT to Port
PIC16CE62X FIGURE 13-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Timeout 32 OSC Timeout Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins FIGURE 13-8: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 13-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
PIC16CE62X FIGURE 13-9: TIMER0 CLOCK TIMING RA4/T0CKI 41 40 42 TMR0 TABLE 13-6: Parameter No. 40 TIMER0 CLOCK REQUIREMENTS Sym Characteristic Tt0H T0CKI High Pulse Width No Prescaler With Prescaler 41 Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42 * † Tt0P T0CKI Period Min Typ† Max Units Conditions 0.5 TCY + 20* — — ns 10* — — ns 0.5 TCY + 20* — — ns 10* — — ns TCY + 40* N — — ns N = prescale value (1, 2, 4, ...
PIC16CE62X 13.6 EEPROM Timing FIGURE 13-10: BUS TIMING DATA TR TF THIGH TLOW SCL TSU:STA THD:DAT TSU:DAT TSU:STO THD:STA SDA IN TSP TAA THD:STA TAA TBUF SDA OUT TABLE 13-7: AC CHARACTERISTICS Parameter Symbol STANDARD MODE Vcc = 4.5 - 5.5V FAST MODE Min. Max. Min. Max.
PIC16CE62X NOTES: DS40182D-page 96 1998-2013 Microchip Technology Inc.
PIC16CE62X 14.0 PACKAGING INFORMATION 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D W2 2 n 1 W1 E A2 A c L A1 eB B1 p B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg.
PIC16CE62X 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c A1 B1 p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .
PIC16CE62X 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16CE62X 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E p E1 D 2 B n 1 h 45 c A2 A L Units Dimension Limits n p MIN A1 INCHES* NOM 18 .050 .099 .091 .008 .407 .295 .454 .020 .033 4 .011 .017 12 12 MAX MILLIMETERS NOM 18 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 11.33 11.53 0.25 0.50 0.41 0.84 0 4 0.23 0.27 0.36 0.
PIC16CE62X 14.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX AABBCDE 18-Lead SOIC (.300") XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE 18-Lead CERDIP Windowed PIC16CE625 -04I/P423 9907CDK Example PIC16CE625 -04I/SO218 9907CDK Example XXXXXXXX XXXXXXXX AABBCDE 20-Lead SSOP Example XXXXXXXXXX XXXXXXXXXX AABBCDE Legend: XX...
PIC16CE62X NOTES: DS40182D-page 102 1998-2013 Microchip Technology Inc.
PIC16CE62X APPENDIX A: CODE FOR ACCESSING EEPROM DATA MEMORY APPENDIX B:REVISION HISTORY Revision D (January 2013) Added a note to each package outline drawing. Please check our web site at www.microchip.com for code availability. 1998-2013 Microchip Technology Inc.
PIC16CE62X NOTES: DS40182D-page 104 1998-2013 Microchip Technology Inc.
PIC16CE62X INDEX A CALL Instruction ................................................................. 69 Clocking Scheme/Instruction Cycle .................................... 10 CLRF Instruction ................................................................. 69 CLRW Instruction ................................................................ 69 CLRWDT Instruction ........................................................... 70 CMCON Register ................................................................
PIC16CE62X Port RB Interrupt ................................................................. 60 PORTA................................................................................ 23 PORTB................................................................................ 26 Power Control/Status Register (PCON) .............................. 55 Power-Down Mode (SLEEP)............................................... 63 Power-On Reset (POR) ......................................................
PIC16XXXXXX FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16XXXXXX FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16CE62X PIC16CE62X PRODUCT IDENTIFICATION SYSTEM To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. PART NO.
PIC16CE62X NOTES: DS40182D-page 110 1998-2013 Microchip Technology Inc.
PIC16CE62X NOTES: 1998-2013 Microchip Technology Inc.
PIC16CE62X DS40182D-page 112 1998-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.
