Datasheet

PIC16C9XX

DS30444E - page 96  1997 Microchip Technology Inc.

13.1.2 MULTIPLEX TIMING GENERATION

The timing generation circuitry will generate 1 to 4 com-

mon clocks based on the display mode selected. The

mode is speciﬁed by bits LMUX1:LMUX0

(LCDCON<1:0>). Table 13-1 shows the formulas for

calculating the frame frequency.

TABLE 13-1: FRAME FREQUENCY

FORMULAS

Multiplex Frame Frequency =

Static Clock source / (128 * (LP3:LP0 + 1))

1/2 Clock source / (128 * (LP3:LP0 + 1))

1/3 Clock source / (96 * (LP3:LP0 + 1))

1/4 Clock source / (128 * (LP3:LP0 + 1))

TABLE 13-2: APPROX. FRAME FREQ IN Hz

USING TIMER1 @ 32.768 kHz OR

Fosc @ 8 MHz

TABLE 13-3: APPROX. FRAME FREQ IN Hz

USING INTERNAL RC OSC @

14 kHz

LP3:LP0 Static 1/2 1/3 1/4

2 85 85 114 85

3 64 64 85 64

4 51 51 68 51

5 43 43 57 43

6 37 37 49 37

7 32 32 43 32

LP3:LP0 Static 1/2 1/3 1/4

0 109 109 146 109

1 55 55 73 55

2 36 36 49 36

3 27 27 36 27