Datasheet

PIC16C9XX
DS30444E - page 90  1997 Microchip Technology Inc.
FIGURE 13-2: LCD MODULE BLOCK DIAGRAM
FIGURE 13-3: LCDPS REGISTER (ADDRESS 10Eh)
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — LP3 LP2 LP1 LP0 R =Readable bit
W =Writable bit
U =Unimplemented bit, Read as ‘0’
-n =Value at POR reset
bit7 bit0
bit 7-4: Unimplemented, read as '0'
bit 3-0: LP3:LP0: Frame Clock Prescale Selection bits
COM3:COM0
32 x 4
Clock
Source
Timing Control
Data Bus
Select
and
Divide
Internal RC osc
Fosc/4
T1CKI
RAM
128
to
32
MUX
SEG<31:0>
TO I/O PADS
TO I/O PADS
LCDCON
LCDPS
LCDSE
LCD
LMUX1:LMUX0 Multiplex Frame Frequency =
00 Static Clock source / (128 * (LP3:LP0 + 1))
01 1/2 Clock source / (128 * (LP3:LP0 + 1))
10 1/3 Clock source / (96 * (LP3:LP0 + 1))
11 1/4 Clock source / (128 * (LP3:LP0 + 1))