Datasheet

 1997 Microchip Technology Inc. DS30444E - page 63
PIC16C9XX
11.0 SYNCHRONOUS SERIAL
PORT (SSP) MODULE
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
2
C)
Refer to Application Note AN578,
"Use of the SSP
Module in the I
2
C Multi-Master Environment."
FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A
P S R/W UA BF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7: SMP: SPI data input sample phase
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Sla
ve Mode
SMP must be cleared when SPI is used in slave mode
bit 6: CKE: SPI Clock Edge Select (Figure 11-5, Figure 11-6, and Figure 11-7)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5: D/A
: Data/Address bit (I
2
C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4: P: Stop bit (I
2
C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit was
detected last)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3: S: Start bit (I
2
C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit was
detected last)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2: R/W
: Read/Write bit information (I
2
C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or A
CK bit.
1 = Read
0 = Write
bit 1: UA: Update Address (10-bit I
2
C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0: BF: Buffer Full Status bit
Receiv
e (SPI and I
2
C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
T
ransmit (I
2
C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty