Datasheet

 1997 Microchip Technology Inc. DS30444E - page 155
PIC16C9XX
TABLE 17-9: SPI MODE REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
70* TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input TCY — — ns
71*
71A*
TscH SCK input high time (slave
mode)
Continuous 1.25TCY +
30
— — ns
Single Byte 40 — — ns
72*
72A*
TscL SCK input low time (slave
mode)
Continuous 1.25TCY +
30
— — ns
Single Byte 40
73* TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge 50 — — ns
74* TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge 50 — — ns
75* TdoR SDO data output rise time — 10 25 ns
76* TdoF SDO data output fall time — 10 25 ns
77* TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns
78* TscR SCK output rise time (master mode) — 10 25 ns
79* TscF SCK output fall time (master mode) — 10 25 ns
80* TscH2doV,
TscL2doV
SDO data output valid after SCK edge — — 50 ns
81* TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge TCY — — ns
82* TssL2doV SDO data output valid after SS↓ edge — — 50 ns
83* TscH2ssH,
TscL2ssH
SS ↑ after SCK edge 1.5TCY + 40 — — ns
84* Tb2b Delay between consecutive bytes 1.5TCY + 40 — — ns
* Characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.