Datasheet

PIC16C9XX
DS30444E - page 114  1997 Microchip Technology Inc.
FIGURE 14-14:INTERRUPT LOGIC
FIGURE 14-15:INT PIN INTERRUPT TIMING
TMR1IF
TMR1IE
TMR2IF
TMR2IE
CCP1IF
CCP1IE
LCDIF
LCDIE
SSPIF
SSPIE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
PEIF
ADIF
ADIE
The A/D module interrupt is implemented on the PIC16C924 only.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTR
UCTION FLOW
PC
Instruction
fetched
Instruction
executed
Interrupt Latency
PC
PC+1
PC+1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC+1)
Inst (PC-1)
Inst (0004h)
Dummy Cycle
Inst (PC)
—
1
4
5
1
Note
1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF can be set anytime during the Q4-Q1 cycles.
2
3