PIC16C9XX 8-Bit CMOS Microcontroller with LCD Driver Devices included in this data sheet: Available in Die Form • PIC16C923 • PIC16C924 Microcontroller Core Features: • • • • • • • • • High performance RISC CPU Only 35 single word instructions to learn 4K x 14 on-chip EPROM program memory 176 x 8 general purpose registers (SRAM) All single cycle instructions (500 ns) except for program branches which are two-cycle Operating speed: DC - 8 MHz clock input DC - 500 ns instruction cycle Interrupt capability
PIC16C9XX RA3 RA2 VSS RA1 RA0 RB2 RB3 MCLR/VPP N/C RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 Pin Diagrams 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 PLCC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Shrink PDIP (750 mil) PIC16C923 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RG7/SEG28 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG
PIC16C9XX RA3/AN3/VREF RA2/AN2 VSS RA1/AN1 RA0/AN0 RB2 RB3 MCLR/VPP N/C RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 Pin Diagrams (Cont.
PIC16C9XX Table of Contents 1.0 General Description..................................................................................................................................................................... 5 2.0 PIC16C9XX Device Varieties ...................................................................................................................................................... 7 3.0 Architectural Overview ..................................................................................
PIC16C9XX 1.0 GENERAL DESCRIPTION The PIC16C9XX is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with an integrated LCD Driver module, in the PIC16CXXX mid-range family. All PICmicro™ microcontrollers employ an advanced RISC architecture. The PIC16CXXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources.
PIC16C9XX TABLE 1-1: PIC16C9XX FAMILY OF DEVICES PIC16C924 PIC16C923 Clock Memory Maximum Frequency of Operation (MHz) 8 8 EPROM Program Memory 4K 4K Data Memory (bytes) 176 176 Timer Module(s) TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 Capture/Compare/PWM Module(s) 1 1 SPI/I2C SPI/I2C Parallel Slave Port — — A/D Converter (8-bit) Channels — 5 LCD Module 4 Com, 32 Seg 4 Com, 32 Seg Serial Port(s) Peripherals (SPI/I2C, USART) Features Interrupt Sources 8 9 I/O Pins 25 25 Input Pins
PIC16C9XX 2.0 PIC16C9XX DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C9XX Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For the PIC16C9XX family, there are two device “types” as indicated in the device number: 1. 2. 2.
PIC16C9XX NOTES: DS30444E - page 8 1997 Microchip Technology Inc.
PIC16C9XX 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory using the same bus.
PIC16C9XX FIGURE 3-1: PIC16C923 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS RAM File Registers 176 x 8 8 Level Stack (13-bit) 4K x 14 8 Data Bus Program Counter EPROM RAM Addr PORTB 9 Addr MUX Instruction reg RB0/INT 7 Direct Addr 8 Indirect Addr RB1-RB7 FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation Oscillator Start-up Timer Power-on Reset PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SD
PIC16C9XX FIGURE 3-2: PIC16C924 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RAM File Registers 176 x 8 8 Level Stack (13-bit) 4K x 14 8 Data Bus Program Counter EPROM RAM Addr PORTB 9 Addr MUX Instruction reg RB0/INT 7 Direct Addr 8 Indirect Addr RB1-RB7 FSR reg STATUS reg 8 3 Power-up Timer Oscillator Start-up Timer Instruction Decode & Control Power-on Reset Timing Generation PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/
PIC16C9XX TABLE 3-1: PIC16C9XX PINOUT DESCRIPTION DIP Pin# PLCC Pin# TQFP Pin# Pin Type Buffer Type OSC1/CLKIN 22 24 14 I ST/CMOS Oscillator crystal input or external clock source input. This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. OSC2/CLKOUT 23 25 15 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode.
PIC16C9XX TABLE 3-1: PIC16C9XX PINOUT DESCRIPTION (Cont.’d) Pin Name COM0 DIP Pin# PLCC Pin# TQFP Pin# Pin Type 59 63 51 L Buffer Type Description Common Driver0 PORTD is a digital input/output port. These pins are also used as LCD Segment and/or Common Drivers. Segment Driver00/Digital Input/Output. RD0/SEG00 29 31 21 I/O/L ST RD1/SEG01 30 32 22 I/O/L ST Segment Driver01/Digital Input/Output. RD2/SEG02 31 33 23 I/O/L ST Segment Driver02/Digital Input/Output.
PIC16C9XX TABLE 3-1: PIC16C9XX PINOUT DESCRIPTION (Cont.’d) DIP Pin# PLCC Pin# TQFP Pin# Pin Type Buffer Type Description 19 20 11 P — LCD Voltage. VDD 20, 60 22, 64 12, 52 P — Digital power. VSS 6, 21 7, 23 13, 62 P — Ground reference. NC — 1 — — — These pins are not internally connected. These pins should be left unconnected.
PIC16C9XX 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-3.
PIC16C9XX NOTES: DS30444E - page 16 1997 Microchip Technology Inc.
PIC16C9XX 4.0 MEMORY ORGANIZATION 4.1 Program Memory Organization The PIC16C9XX family has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 4K x 14 (0000h-0FFFh) is physically implemented. Accessing a location above the physically implemented addresses will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.
PIC16C9XX FIGURE 4-2: REGISTER FILE MAP File Address Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRES(2) ADCON0(2) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.
PIC16C9XX 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. The special function registers can be classified into two sets (core and peripheral).
PIC16C9XX TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (Cont.
PIC16C9XX TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (Cont.
PIC16C9XX TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (Cont.
PIC16C9XX 4.2.2.1 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the “Instruction Set Summary.” STATUS REGISTER The STATUS register, shown in Figure 4-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.
PIC16C9XX 4.2.2.2 OPTION REGISTER Note: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT pin interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 4-4: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16C9XX 4.2.2.3 INTCON REGISTER Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and external RB0/INT pin interrupts. FIGURE 4-5: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PIC16C9XX 4.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the peripheral interrupts. FIGURE 4-6: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC16C9XX 4.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the peripheral interrupts. FIGURE 4-7: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16C9XX 4.2.2.6 For various reset conditions see Table 14-4 and Table 14-5. PCON REGISTER The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset.
PIC16C9XX 4.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-9 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16C9XX 4.5 Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are used). EXAMPLE 4-1: The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register (FSR).
PIC16C9XX 5.0 PORTS FIGURE 5-1: Some pins for these ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Data bus 5.1 WR Port PORTA and TRISA Register The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers.
PIC16C9XX TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 (1) bit0 TTL Input/output or analog input RA1/AN1 (1) bit1 TTL Input/output or analog input RA2/AN2(1) bit2 TTL Input/output or analog input bit3 TTL Input/output or analog input or VREF bit4 ST Input/output or external clock input for Timer0 Output is open drain type RA3/AN3/V REF(1) RA4/T0CKI TTL Input/output or analog input or slave select input for synchronous serial port RA5/AN4/SS (1) bit5 Legend: TTL = T
PIC16C9XX 5.2 PORTB and TRISB Register PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s). EXAMPLE 5-2: This interrupt can wake the device from SLEEP.
PIC16C9XX TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit0 TTL/ST Input/output pin or external interrupt input. Internal software programmable weak pull-up. This buffer is a Schmitt Trigger input when configured as the external interrupt. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
PIC16C9XX 5.3 PORTC and TRISC Register FIGURE 5-5: PORTC is an 6-bit bi-directional port. Each pin is individually configurable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers. VDD RBPU(2) weak P pull-up Data Latch D Q Data bus When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin.
PIC16C9XX 5.4 PORTD and TRISD Registers FIGURE 5-6: PORTD is an 8-bit port with Schmitt Trigger input buffers. The first five pins are configurable as general purpose I/O pins or LCD segment drivers. Pins RD5, RD6 and RD7 can be digital inputs or LCD segment or common drivers. TRISD controls the direction of pins RD0 through RD4 when PORTD is configured as a digital port. Note: On a Power-on Reset these pins are configured as LCD segment drivers.
PIC16C9XX FIGURE 5-7: PORTD<7:5> BLOCK DIAGRAM LCD Segment Data LCD Segment Output Enable LCD Common Data LCD Common Output Enable Digital Input/ LCD Output pin LCDSE Schmitt Trigger input buffer Data Bus Q D EN EN RD PORT VDD RD TRIS TABLE 5-7: PORTD FUNCTIONS Name Bit# Buffer Type RD0/SEG00 bit0 ST Input/output port pin or Segment Driver00 RD1/SEG01 bit1 ST Input/output port pin or Segment Driver01 RD2/SEG02 bit2 ST Input/output port pin or Segment Driver02 RD3/SEG03 bit3 ST
PIC16C9XX 5.5 PORTE and TRISE Register FIGURE 5-8: PORTE is an digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have Schmitt Trigger input buffers. PORTE BLOCK DIAGRAM LCD Segment Data LCD Segment Output Enable Note 1: On a Power-on Reset these pins are configured as LCD segment drivers. LCD Common Data Note 2: To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared.
PIC16C9XX 5.6 PORTF and TRISF Register FIGURE 5-9: PORTF is an digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have Schmitt Trigger input buffers. LCD Segment Data LCD Segment Output Enable Note 1: On a Power-on Reset these pins are configured as LCD segment drivers. LCD Common Data Note 2: To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared.
PIC16C9XX 5.7 PORTG and TRISG Register FIGURE 5-10: PORTG BLOCK DIAGRAM PORTG is an digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have Schmitt Trigger input buffers. LCD Segment Data LCD Segment Output Enable Note 1: On a Power-on Reset these pins are configured as LCD segment drivers. LCD Common Data Note 2: To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared.
PIC16C9XX 5.8 I/O Programming Considerations 5.8.1 BI-DIRECTIONAL I/O PORTS EXAMPLE 5-8: Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
PIC16C9XX NOTES: DS30444E - page 42 1997 Microchip Technology Inc.
PIC16C9XX 6.0 OVERVIEW OF TIMER MODULES Each module can generate an interrupt to indicate that an event has occurred (e.g. timer overflow). Each of these modules is explained in full detail in the following sections. The timer modules are: • Timer0 Module (Section 7.0) • Timer1 Module (Section 8.0) • Timer2 Module (Section 9.0) 6.1 Timer0 Overview chronous Serial Port (SSP). The prescaler option allows Timer2 to increment at the following rates: 1:1, 1:4, 1:16.
PIC16C9XX NOTES: DS30444E - page 44 1997 Microchip Technology Inc.
PIC16C9XX 7.0 TIMER0 MODULE bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. The Timer0 module has the following features: • • • • • • 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer.
PIC16C9XX FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 Instruction Fetch PC PC+1 MOVWF TMR0 MOVF TMR0,W Instruction Execute PC+4 PC+5 MOVF TMR0,W PC+6 MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 PC+6 NT0+1 NT0 Write TMR0 executed FIGURE 7-4: PC+3 MOVF TMR0,W T0+1 T0 TMR0 PC+2 MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 rea
PIC16C9XX 7.2 Using Timer0 with an External Clock caler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns.
PIC16C9XX 7.3 Prescaler When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler count. When assigned to WDT, a CLRWDT instruction will clear the prescaler count along with the Watchdog Timer. The prescaler is not readable or writable. An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (Figure 7-6).
PIC16C9XX 7.3.1 SWITCHING PRESCALER ASSIGNMENT Note: The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program execution. EXAMPLE 7-1: To avoid an unintended device RESET, the following instruction sequence (shown in Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This precaution must be followed even if the WDT is disabled.
PIC16C9XX NOTES: DS30444E - page 50 1997 Microchip Technology Inc.
PIC16C9XX 8.0 TIMER1 MODULE Timer1 is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
PIC16C9XX 8.1 Timer1 Operation in Timer Mode 8.2.1 Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is Fosc/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect since the internal clock is always in sync. 8.2 When an external clock input is used for Timer1 in synchronized counter mode, it must meet certain requirements. The external clock requirement is due to internal phase clock (Tosc) synchronization.
PIC16C9XX 8.3 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow which will wake-up the processor. However, special precautions in software are needed to read-from or write-to the Timer1 register pair (TMR1H:TMR1L) (Section 8.3.2).
PIC16C9XX 8.5 Resetting Timer1 using the CCP Trigger Output 8.6 If the CCP1 module is configured in compare mode to generate a “special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1. Note: Resetting of Timer1 Register Pair (TMR1H:TMR1L) TMR1H and TMR1L registers are not reset on a POR or any other reset except by the CCP1 special event trigger. T1CON register is reset to 00h on a Power-on Reset. In any other reset, the register is unaffected.
PIC16C9XX 9.0 TIMER2 MODULE 9.1 Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16 (selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>)). The Timer2 module has an 8-bit period register, PR2.
PIC16C9XX TABLE 9-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on Power-on Reset Value on all other resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh, 8Bh, 10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0Ch PIR1 LCDIF ADIF(1) — — SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 8Ch PIE1 LCDIE ADIE(1) — — SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 11h TMR2 12h T2CON 92h PR2 0000 0000 0000 0000 Timer2 module’s
PIC16C9XX 10.0 CAPTURE/COMPARE/PWM (CCP) MODULE For use of the CCP module, refer to the Embedded Control Handbook, "Using the CCP Modules" (AN594). The CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register, or as a PWM master/slave duty cycle register. Table 10-1 shows the timer resources used by the CCP module.
PIC16C9XX 10.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1 (Figure 10-2). An event is defined as: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software.
PIC16C9XX 10.2.1 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 10.2.2 FIGURE 10-4: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty cycle registers CCPR1L SOFTWARE INTERRUPT MODE When Generate Software Interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). CCPR1H (Slave) R Comparator 10.2.
PIC16C9XX Note: 10.3.2 EXAMPLE 10-2: PWM PERIOD AND DUTY CYCLE CALCULATION The Timer2 postscaler (Section 9.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. Desired PWM frequency is 31.25 kHz, Fosc = 8 MHz TMR2 prescale = 1 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits.
PIC16C9XX TABLE 10-3: REGISTERS ASSOCIATED WITH TIMER1, CAPTURE AND COMPARE Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other Resets 0Bh, 8Bh, 10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 LCDIF ADIF(1) — — SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 LCDIE (1) — — SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 8Ch PIE1 ADIE 87h TRISC --11 1111 --11 1111 0Eh T
PIC16C9XX NOTES: DS30444E - page 62 1997 Microchip Technology Inc.
PIC16C9XX 11.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE play drivers, A/D converters, etc. The SSP module can operate in one of two modes: The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, dis- • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I 2C) Refer to Application Note AN578, "Use of the SSP Module in the I 2C Multi-Master Environment.
PIC16C9XX FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Indicator bi
PIC16C9XX 11.1 SPI Mode The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: • Serial Data Out (SDO) RC5/SDO • Serial Data In (SDI) RC4/SDI • Serial Clock (SCK) RC3/SCK Additionally a fourth pin may be used when in a slave mode of operation: • Slave Select (SS) RA5/AN4/SS (the AN4 function is implemented on the PIC16C924 only) When initializing the SPI, several options need to be specified.
PIC16C9XX To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed.
PIC16C9XX The SS pin allows a synchronous slave mode. The SPI must be in slave mode (SSPCON<3:0> = 04h) and the TRISA<5> bit must be set for the synchronous slave mode to be enabled. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/ pull-down resistors may be desirable, depending on the application.
PIC16C9XX FIGURE 11-7: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS (not optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit6 bit7 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF TABLE 11-1: REGISTERS ASSOCIATED WITH SPI OPERATION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 0Bh, 8Bh, 10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 LCDIF ADIF(1) — — SSPIF
PIC16C9XX I 2C Overview 11.2 This section provides an overview of the Inter-Integrated Circuit (I 2C) bus, with Section 11.3 discussing the operation of the SSP module in I 2C mode. The I 2C bus is a two-wire serial interface developed by the Philips Corporation. The original specification, or standard mode, was for data transfers of up to 100 Kbps. An enhanced specification, or fast mode is not supported. This device will communicate with fast mode devices if attached to the same bus.
PIC16C9XX ADDRESSING I 2C DEVICES 11.2.2 FIGURE 11-11: SLAVE-RECEIVER ACKNOWLEDGE There are two address formats. The simplest is the 7-bit address format with a R/W bit (Figure 11-9). The more complex is the 10-bit address with a R/W bit (Figure 11-10). For 10-bit address format, two bytes must be transmitted with the first five bits specifying this to be a 10-bit address.
PIC16C9XX is high), but occurs after a data transfer acknowledge pulse (not the bus-free state). This allows a master to send “commands” to the slave and then receive the requested information or to address a different slave device. This sequence is shown in Figure 11-15. Figure 11-13 and Figure 11-14 show Master-transmitter and Master-receiver data transfer sequences. When a master does not wish to relinquish the bus (by generating a STOP condition), a repeated START condition (Sr) must be generated.
PIC16C9XX 11.2.4 MULTI-MASTER 11.2.4.2 Clock Synchronization The I2C protocol allows a system to have more than one master. This is called multi-master. When two or more masters try to transfer data at the same time, arbitration and synchronization occur. 11.2.4.1 ARBITRATION Arbitration takes place on the SDA line, while the SCL line is high. The master which transmits a high when the other master transmits a low loses arbitration (Figure 11-16), and turns off its data output stage.
PIC16C9XX 11.3 SSP I 2C Operation The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/SCK/SCL pin, which is the clock (SCL), and the RC4/SDI/SDA pin, which is the data (SDA).
PIC16C9XX 11.3.1 SLAVE MODE In slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter). When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register.
PIC16C9XX 11.3.1.2 An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given.
PIC16C9XX 11.3.1.3 An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. TRANSMISSION When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register.
PIC16C9XX 11.3.2 11.3.3 MASTER MODE MULTI-MASTER MODE In multi-master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP and START bits will toggle based on the start and stop conditions. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle with both the S and P bits clear.
PIC16C9XX FIGURE 11-21: OPERATION OF THE I 2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE IDLE_MODE (7-bit): if (Addr_match) { Set interrupt; if (R/W = 1) { Send ACK = 0; set XMIT_MODE; } else if (R/W = 0) set RCV_MODE; } RCV_MODE: if ((SSPBUF=Full) OR (SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { transfer SSPSR → SSPBUF; send ACK = 0; } Receive 8-bits in SSPSR; Set interrupt; XMIT_MODE: While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low; Send byte; Set interrupt; if ( ACK Received = 1) { End of
PIC16C9XX 12.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has three registers. These registers are: • A/D Result Register (ADRES) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 (ADCON1) This section applies to the PIC16C924 only. The analog-to-digital (A/D) converter module has five inputs. The ADCON0 register, shown in Figure 12-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 12-2, configures the functions of the port pins.
PIC16C9XX FIGURE 12-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCFG2 PCFG1 PCFG0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 VREF 000 A A A A A AVDD 001 A A A A VREF RA3 010 A A A A A AVDD 011 A A A A VREF RA3 100 A A D D A AVD
PIC16C9XX FIGURE 12-3: A/D BLOCK DIAGRAM CHS2:CHS0 100 VAIN 011 (Input voltage) RA5/AN4 RA3/AN3/VREF 010 RA2/AN2 A/D Converter 001 RA1/AN1 AVDD 000 RA0/AN0 000 or 010 or 100 VREF (Reference voltage) 001 or 011 PCFG2:PCFG0 1997 Microchip Technology Inc.
PIC16C9XX 12.1 A/D Acquisition Requirements Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD.
PIC16C9XX 12.2 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5 TAD per 8-bit conversion. The source of the A/D conversion clock is software selected. The four possible options for TAD are: • • • • 2TOSC 8TOSC 32TOSC Internal RC oscillator 12.3 Configuring Analog Port Pins The ADCON1 and TRISA registers control the operation of the A/D port pins.
PIC16C9XX 12.4 A/D Conversions Example 12-2 show how to perform an A/D conversion. The RA pins are configured as analog inputs. The analog reference (VREF) is the device VDD. The A/D interrupt is enabled, and the A/D conversion clock is FRC. The conversion is performed on the RA0 pin (channel0). Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. Clearing the GO/DONE bit during a conversion will abort the current conversion.
PIC16C9XX 12.4.1 FASTER CONVERSION - LOWER RESOLUTION TRADE-OFF Not all applications require a result with 8-bits of resolution, but may instead require a faster conversion time. The A/D module allows users to make the trade-off of conversion speed to resolution. Regardless of the resolution required, the acquisition time is the same.
PIC16C9XX 12.5 A/D Operation During Sleep The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed the GO/DONE bit will be cleared, and the result loaded into the ADRES register.
PIC16C9XX Use of the CCP Trigger An A/D conversion can be started by the “special event trigger” of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero.
PIC16C9XX FIGURE 12-6: FLOWCHART OF A/D OPERATION ADON = 0 Yes ADON = 0? No Acquire Selected Channel Yes GO = 0? No Yes A/D Clock = RC? SLEEP Yes Instruction? Start of A/D Conversion Delayed 1 Instruction Cycle Finish Conversion GO = 0 ADIF = 1 No No Yes Device in SLEEP? Abort Conversion GO = 0 ADIF = 0 Wake-up Yes From Sleep? Finish Conversion GO = 0 ADIF = 1 Wait 2 TAD No No SLEEP Power-down A/D Finish Conversion GO = 0 ADIF = 1 Stay in Sleep Power-down A/D Wait 2 TAD Wait 2 TAD T
PIC16C9XX 13.0 LCD MODULE Once the module is initialized for the LCD panel, the individual bits of the LCD data registers are cleared/set to represent a clear/dark pixel respectively. The LCD module generates the timing control to drive a static or multiplexed LCD panel, with support for up to 32 segments multiplexed with up to 4 commons. It also provides control of the LCD pixel data. Once the module is configured, the LCDEN (LCDCON<7>) bit is used to enable or disable the LCD module.
PIC16C9XX FIGURE 13-2: LCD MODULE BLOCK DIAGRAM 128 LCD RAM 32 x 4 Data Bus to SEG<31:0> TO I/O PADS 32 MUX Timing Control LCDCON COM3:COM0 LCDPS TO I/O PADS LCDSE Internal RC osc T1CKI Fosc/4 Clock Source Select and Divide FIGURE 13-3: LCDPS REGISTER (ADDRESS 10Eh) U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — LP3 LP2 LP1 LP0 bit7 bit0 R =Readable bit W =Writable bit U =Unimplemented bit, Read as ‘0’ -n =Value at POR reset bit 7-4: Unimplemented, read as '0' bit 3-0: LP3:L
PIC16C9XX FIGURE 13-4: WAVEFORMS IN STATIC DRIVE V1 COM0 V0 COM0 V1 SEG0 V0 V1 SEG1 V0 V1 COM0-SEG0 V0 -V1 SEG1 SEG0 SEG2 SEG7 SEG6 SEG5 SEG4 SEG3 COM0-SEG1 1997 Microchip Technology Inc.
PIC16C9XX FIGURE 13-5: WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 COM1 V0 V3 COM0 V2 COM1 V1 V0 V3 V2 SEG0 V1 SEG3 SEG2 SEG1 SEG0 V0 V3 V2 SEG1 V1 V0 V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 -V1 1 Frame -V2 -V3 DS30444E - page 92 1997 Microchip Technology Inc.
PIC16C9XX FIGURE 13-6: WAVEFORMS IN 1/3 MUX, 1/3 BIAS V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 SEG0 V0 SEG0 SEG1 SEG2 V1 V3 V2 SEG1 V1 V0 V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 -V1 -V2 -V3 1 Frame 1997 Microchip Technology Inc.
PIC16C9XX FIGURE 13-7: WAVEFORMS IN 1/4 MUX, 1/3 BIAS COM3 COM2 COM0 V3 V2 V1 V0 COM1 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 SEG0 SEG1 COM0 1 Frame DS30444E - page 94 1997 Microchip Technology Inc.
PIC16C9XX 13.1 LCD Timing The LCD module has 3 possible clock source inputs and supports static, 1/2, 1/3, and 1/4 multiplexing. 13.1.1 TIMING CLOCK SOURCE SELECTION The clock sources for the LCD timing generation are: • Internal RC oscillator • Timer1 oscillator • System clock divided by 256 The first timing source is an internal RC oscillator which runs at a nominal frequency of 14 kHz.
PIC16C9XX 13.1.2 MULTIPLEX TIMING GENERATION The timing generation circuitry will generate 1 to 4 common clocks based on the display mode selected. The mode is specified by bits LMUX1:LMUX0 (LCDCON<1:0>). Table 13-1 shows the formulas for calculating the frame frequency.
PIC16C9XX 13.2 LCD Interrupts The LCD timing generation provides an interrupt that defines the LCD frame timing. This interrupt can be used to coordinate the writing of the pixel data with the start of a new frame. Writing pixel data at the frame boundary allows a visually crisp transition of the image. This interrupt can also be used to synchronize external events to the LCD.
PIC16C9XX 13.3 Pixel Control 13.3.1 LCDD (PIXEL DATA) REGISTERS Table 13-4 shows the correlation of each bit in the LCDD registers to the respective common and segment signals. The pixel registers contain bits which define the state of each pixel. Each bit defines one unique pixel. Any LCD pixel location not being used for display can be used as general purpose RAM.
PIC16C9XX 13.4 Operation During Sleep The LCD module can operate during sleep. The selection is controlled by bit SLPEN (LCDCON<6>). Setting the SLPEN bit allows the LCD module to go to sleep. Clearing the SLPEN bit allows the module to continue to operate during sleep. If a SLEEP instruction is executed and SLPEN = '1', the LCD module will cease all functions and go into a very low current consumption mode.
PIC16C9XX 13.4.1 EXAMPLE 13-1: STATIC MUX WITH 32 SEGMENTS SEGMENT ENABLES The LCDSE register is used to select the pin function for groups of pins. The selection allows each group of pins to operate as either LCD drivers or digital only pins. To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared. BCF BSF BCF BCF MOVLW MOVWF . . . If the pin is a digital I/O the corresponding TRIS bit controls the data direction.
PIC16C9XX 13.5 Voltage Generation There are two methods for LCD voltage generation, internal charge pump, or external resistor ladder. 2*VLCD1 and VLCD3 = 3 * VLCD1. When the charge pump is not operating, Vlcd3 will be internally tied to VDD. See the Electrical Specifications section for charge pump capacitor and potentiometer values. 13.5.1 13.5.2 CHARGE PUMP The LCD charge pump is shown in Figure 13-13. The 1.0V - 2.3V regulator will establish a stable base voltage from the varying battery voltage.
PIC16C9XX 13.6 Configuring the LCD Module The following is the sequence of steps to follow to configure the LCD module. 1. Select the frame clock prescale using bits LP3:LP0 (LCDPS<3:0>). 2. Configure the appropriate pins to function as segment drivers using the LCDSE register. 3. Configure the LCD module for the following using the LCDCON register. - Multiplex mode and Bias, bits LMUX1:LMUX0 - Timing source, bits CS1:CS0 - Voltage generation, bit VGEN - Sleep mode, bit SLPEN 4.
PIC16C9XX 14.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. The PIC16CXXX family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC16C9XX 14.2 Oscillator Configurations 14.2.1 OSCILLATOR TYPES TABLE 14-1: CERAMIC RESONATORS Ranges Tested: The PIC16CXXX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC 14.2.
PIC16C9XX 14.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. Figure 14-4 shows implementation of a parallel resonant oscillator circuit.
PIC16C9XX 14.3 Reset The PIC16CXX differentiates between various kinds of reset: • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (normal operation) the resumption of normal operation. The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 14-4. These bits are used in software to determine the nature of the reset. See Table 14-6 for a full description of reset states of all registers.
PIC16C9XX 14.4 14.4.1 Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) 14.4.3 The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. POWER-ON RESET (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V).
PIC16C9XX TABLE 14-4: STATUS BITS AND THEIR SIGNIFICANCE POR TO PD 0 1 1 Power-on Reset 0 0 x Illegal, TO is set on POR 0 x 0 Illegal, PD is set on POR 1 0 1 WDT Reset 1 0 0 WDT Wake-up 1 u u MCLR Reset during normal operation 1 1 0 Legend: u = unchanged, x = unknown MCLR Reset during SLEEP or interrupt wake-up from SLEEP TABLE 14-5: RESET CONDITION FOR SPECIAL REGISTERS Program Counter Condition STATUS Register Register PCON Power-on Reset 000h 0001 1xxx ---- --0- MCLR
PIC16C9XX TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.
PIC16C9XX TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.
PIC16C9XX FIGURE 14-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 14-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 14-10:TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 1997 Microchip Technology Inc.
PIC16C9XX FIGURE 14-11:EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 14-12:EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD D VDD 33k VDD 10k R R1 40k MCLR C MCLR PIC16CXXX PIC16CXXX Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. Note 1: This circuit will activate reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage.
PIC16C9XX 14.
PIC16C9XX FIGURE 14-14:INTERRUPT LOGIC TMR1IF TMR1IE Wake-up (If in SLEEP mode) T0IF T0IE INTF INTE TMR2IF TMR2IE Interrupt to CPU RBIF RBIE LCDIF LCDIE PEIF PEIE GIE CCP1IF CCP1IE SSPIF SSPIE ADIF ADIE The A/D module interrupt is implemented on the PIC16C924 only.
PIC16C9XX 14.5.1 14.6 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt.
PIC16C9XX 14.7 Watchdog Timer (WDT) assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin.
PIC16C9XX 14.8 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC16C9XX FIGURE 14-18:WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = SLEEP Instruction executed Inst(PC - 1) Note 14.9 1: 2: 3: 4: PC+1 PC+2 Inst(PC + 2) SLEEP Inst(PC + 1) 14.
PIC16C9XX 15.0 INSTRUCTION SET SUMMARY Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 15-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 15-1 shows the opcode field descriptions.
PIC16C9XX TABLE 15-2: PIC16CXXX INSTRUCTION SET Mnemonic, Operands Description 14-Bit Opcode Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to
PIC16C9XX 15.1 Instruction Descriptions ADDLW Add Literal and W ADDWF Add W and f Syntax: [label] ADDLW Syntax: [label] ADDWF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) + k → (W) 0 ≤ f ≤ 127 d ∈ [0,1] Status Affected: C, DC, Z Operation: (W) + (f) → (destination) Status Affected: C, DC, Z 11 Encoding: Description: 1 Cycles: 1 Example: kkkk kkkk The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
PIC16C9XX ANDLW AND Literal with W ANDWF AND W with f Syntax: [label] ANDLW Syntax: [label] ANDWF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .AND. (k) → (W) 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .AND. (f) → (destination) Status Affected: Z Status Affected: Z 11 Encoding: 1001 k kkkk kkkk 00 Encoding: Description: The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register.
PIC16C9XX BTFSC Bit Test, Skip if Clear Syntax: [label] BTFSC f,b 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 1 → (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None BSF Bit Set f Syntax: [label] BSF Operands: 01 Encoding: f,b 01bb bfff Description: Bit 'b' in register 'f' is set.
PIC16C9XX BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [label] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ k ≤ 2047 Operation: Operation: skip if (f) = 1 Status Affected: None (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Status Affected: None 01 Encoding: Description: bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is executed.
PIC16C9XX CLRF Clear f Syntax: [label] CLRF Operands: 0 ≤ f ≤ 127 Operation: 00h → (f) 1→Z Status Affected: Z 00 Encoding: f 0001 1fff ffff CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h → (W) 1→Z Status Affected: Z 00 Encoding: 0001 0xxx xxxx Description: The contents of register 'f' are cleared and the Z bit is set. Description: W register is cleared. Zero bit (Z) is set.
PIC16C9XX CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Status Affected: 00 Description: 0000 0110 1 Cycles: 1 Q Cycle Activity: Syntax: [ label ] COMF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (destination) Status Affected: Z 00 Q1 Q2 Q3 Q4 NoOperation Process data Clear WDT Counter 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W.
PIC16C9XX DECFSZ Decrement f, Skip if 0 GOTO Unconditional Branch Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 2047 Operation: Operation: (f) - 1 → (destination); skip if result = 0 k → PC<10:0> PCLATH<4:3> → PC<12:11> Status Affected: None Status Affected: None 00 Encoding: Description: Cycles: 1(2) If Skip: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Q3 NoNoNoOperation Operation Operation Examp
PIC16C9XX INCF Increment f INCFSZ Increment f, Skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (destination) Operation: Status Affected: Z (f) + 1 → (destination), skip if result = 0 Status Affected: None 00 Encoding: Description: INCF f,d 1010 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register.
PIC16C9XX IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .OR. k → (W) 0 ≤ f ≤ 127 d ∈ [0,1] Status Affected: Z Operation: (W) .OR. (f) → (destination) Status Affected: Z 11 Encoding: Description: 1 Cycles: 1 Example 1000 kkkk kkkk The contents of the W register is OR’ed with the eight bit literal 'k'. The result is placed in the W register.
PIC16C9XX MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (destination) Status Affected: Z Description: 1000 dfff 1 Cycles: 1 Q Cycle Activity: Syntax: [ label ] Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) Status Affected: None 00 MOVWF 0000 f 1fff Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Description: Move data from W register to register 'f'.
PIC16C9XX NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS → PC, 1 → GIE Status Affected: None 00 Encoding: NOP 0000 Description: No operation. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode 0xx0 0000 00 Encoding: Q2 Q3 0000 0000 1001 Description: Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC.
PIC16C9XX RETLW Return with Literal in W RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W); TOS → PC Operation: TOS → PC Status Affected: None Status Affected: None RETLW k Encoding: Description: 01xx kkkk Words: 1 2 Cycles: Cycles: 2 Q Cycle Activity: 1st Cycle 2nd Cycle Decode Read literal 'k' Q3 1000 Return from subroutine.
PIC16C9XX RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C 00 Encoding: Description: RLF f,d 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register.
PIC16C9XX SLEEP SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Syntax: [ label ] Operands: None Operands: 0 ≤ k ≤ 255 Operation: 00h → WDT, 0 → WDT prescaler, 1 → TO, 0 → PD Operation: k - (W) → (W) Status Affected: C, DC, Z TO, PD Description: The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.
PIC16C9XX SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] Syntax: [ label ] SWAPF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (destination) Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Status Affected: None SUBWF f,d Status Affected: C, DC, Z Encoding: Description: 00 1 Cycles: 1 Example 1: dfff ffff Subtract (2’s complement method) W register from register 'f'.
PIC16C9XX XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [label] Syntax: [label] Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .XOR. k → (W) 0 ≤ f ≤ 127 d ∈ [0,1] Status Affected: Z Operation: (W) .XOR. (f) → (destination) Status Affected: Z Encoding: Description: 11 1 Cycles: 1 Example: 1010 kkkk kkkk The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.
PIC16C9XX 16.0 DEVELOPMENT SUPPORT 16.
PIC16C9XX 16.6 PICDEM-1 Low-Cost PICmicro Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs.
PIC16C9XX MPASM has the following features to assist in developing software for specific use applications. • Provides translation of Assembler source code to object code for all Microchip microcontrollers. • Macro assembly capability. • Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems. • Supports Hex (default), Decimal and Octal source and listing formats.
Emulator Products Software Tools DS30444E - page 140 Programmers ✔ KEELOQ Evaluation Kit PICDEM-3 PICDEM-2 PICDEM-1 SEEVAL Designers Kit KEELOQ Programmer PRO MATE II Universal Programmer PICSTART Plus Low-Cost Universal Dev. Kit PICSTART Lite Ultra Low-Cost Dev. Kit Total Endurance Software Model ✔ ✔ ✔ fuzzyTECH-MP Explorer/Edition Fuzzy Logic Dev.
PIC16C9XX 17.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias............................................................................................................ .-55˚C to +125˚C Storage temperature .............................................................................................................................. -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.
PIC16C9XX 17.1 DC Characteristics: PIC16C923/924-04 (Commercial, Industrial) PIC16C923/924-08 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units Conditions D001 Supply Voltage D001A VDD 4.0 4.5 - 6.0 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.
PIC16C9XX 17.2 DC Characteristics: PIC16LC923/924-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units Conditions D001 Supply Voltage VDD 2.5 - 6.0 V D002* RAM Data Retention Voltage (Note 1) VDR - 1.
PIC16C9XX 17.3 DC Characteristics: DC CHARACTERISTICS Param No.
PIC16C9XX FIGURE 17-1: LCD VOLTAGE WAVEFORM D223 D224 VLCD3 VLCD2 VLCD1 VSS TABLE 17-2: LCD MODULE ELECTRICAL SPECIFICATIONS Parameter No. Sym D200 VLCD3 D201 Min Typ† Max Units LCD Voltage on pin VLCD3 VDD - 0.3 — Vss + 7.0 V VLCD2 LCD Voltage on pin VLCD2 — — VLCD3 V D202 VLCD1 LCD Voltage on pin VLCD1 — — VDD V D220* VOH Output High Voltage Max VLCDN 0.
PIC16C9XX 17.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16C9XX FIGURE 17-2: LOAD CONDITIONS Load condition 2 Load condition 1 VDD/2 RL CL Pin VSS CL Pin VSS RL = 464Ω CL = 50 pF 15 pF 1997 Microchip Technology Inc. for all pins except OSC2 unless otherwise noted.
PIC16C9XX 17.5 Timing Diagrams and Specifications FIGURE 17-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 17-4: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter No. Sym Characteristic Fosc External CLKIN Frequency (Note 1) Min Typ† Max Units Conditions DC — 4 MHz XT and RC osc mode DC — 8 MHz HS osc mode DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.
PIC16C9XX FIGURE 17-4: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Refer to Figure 17-2 for load conditions. TABLE 17-5: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No.
PIC16C9XX FIGURE 17-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Refer to Figure 17-2 for load conditions. TABLE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
PIC16C9XX FIGURE 17-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Refer to Figure 17-2 for load conditions. TABLE 17-7: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width No Prescaler T0CKI Low Pulse Width With Prescaler No Prescaler With Prescaler 41* 42* 45* 46* 47* 48 * † Tt0L Min Typ† Max 0.
PIC16C9XX FIGURE 17-7: CAPTURE/COMPARE/PWM TIMINGS RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Refer to Figure 17-2 for load conditions. TABLE 17-8: CAPTURE/COMPARE/PWM REQUIREMENTS Parameter No.
PIC16C9XX FIGURE 17-8: SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Refer to Figure 17-2 for load conditions. FIGURE 17-9: SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO BIT6 - - - - - -1 MSb LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 Refer to Figure 17-2 for load conditions. 1997 Microchip Technology Inc.
PIC16C9XX FIGURE 17-10:SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb BIT6 - - - - - -1 77 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Refer to Figure 17-2 for load conditions. FIGURE 17-11:SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSb BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN 77 BIT6 - - - -1 LSb IN 74 Refer to Figure 17-2 for load conditions.
PIC16C9XX TABLE 17-9: SPI MODE REQUIREMENTS Param No. 70* 71* Sym TssL2scH, TssL2scL TscH Characteristic Min Typ† Max Units SS↓ to SCK↓ or SCK↑ input TCY — — ns 1.25TCY + 30 40 1.
PIC16C9XX FIGURE 17-12:I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA START Condition STOP Condition Refer to Figure 17-2 for load conditions. TABLE 17-10:I2C BUS START/STOP BITS REQUIREMENTS Parameter No. Sym 90* TSU:STA Characteristic START condition Setup time 91* THD:STA START condition Hold time 92* TSU:STO STOP condition Setup time 93* THD:STO STOP condition Hold time * Characterized but not tested.
PIC16C9XX FIGURE 17-13:I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Refer to Figure 17-2 for load conditions. TABLE 17-11:I2C BUS DATA REQUIREMENTS Parameter No.
PIC16C9XX TABLE 17-12:A/D CONVERTER CHARACTERISTICS: PIC16C924-04 (COMMERCIAL, INDUSTRIAL) PIC16LC924-04 (COMMERCIAL, INDUSTRIAL) Param Sym Characteristic No. A01 NR A02 Resolution EABS Total Absolute error Typ† Max Units Conditions — — 8-bits bit — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A03 EIL A04 EDL Differential linearity error — — <±1 LSb VREF = VDD = 5.
PIC16C9XX FIGURE 17-14:A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (TOSC/2) (1) 131 Q4 130 A/D CLK 132 7 A/D DATA 6 5 4 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 17-13:A/D CONVERSION REQUIREMENTS Param No. 130 Sym Characteristic TAD A/D clock period Min Typ† Max PIC16C924 1.
PIC16C9XX NOTES: DS30444E - page 160 1997 Microchip Technology Inc.
PIC16C9XX 18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
PIC16C9XX FIGURE 18-7: TYPICAL IPD vs. VDD (LCD ON(1), TIMER1 (32 kHz(2)), RC MODE @ 25°C) 60 90 55 80 50 70 45 60 IPD(µA) IPD(µA) FIGURE 18-5: TYPICAL IPD vs. VDD (LCD ON(1), INTERNAL RC(2), RC MODE @ 25°C) 40 40 35 30 30 2.5 3.0 3.5 4.0 4.5 5.0 VDD (VOLTS) 5.5 6.0 20 C Spec @ 4.0V = 41 LC Spec @ 3.0V = 37 10 0 2.5 FIGURE 18-6: MAXIMUM IPD vs. VDD (LCD ON (32 kHz(1)), INTERNAL RC (32 kHz(2)), RC MODE -40°C TO +85°C) IPD(µA) 65 60 180 55 160 50 3.5 4.0 4.5 5.0 VDD (VOLTS) 5.
PIC16C9XX FIGURE 18-9: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD FIGURE 18-12:TYPICAL IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, RC MODE) Cext = 22 pF, T = 25°C 6.0 5.5 5.0 30 R = 5k 25 4.0 3.5 20 3.0 R = 10k 2.5 IPD(µA) Fosc(MHz) 4.5 2.0 10 1.5 1.0 R = 100k 5 0.5 0.0 2.5 15 3.0 3.5 4.0 4.5 VDD (VOLTS) 5.0 5.5 0 2.5 6.0 3.0 3.5 4.0 4.5 VDD (VOLTS) 5.0 5.5 6.0 Shaded area is beyond recommended range. FIGURE 18-13:MAXIMUM IPD vs.
PIC16C9XX FIGURE 18-14:TYPICAL IDD vs. FREQUENCY (RC MODE @ 20 pF, 25°C) 2500 6.0V 5.5V IDD(µA) 2000 5.0V 4.5V 4.0V 1500 3.5V 3.0V 1000 2.5V 500 0 0.0 1.00 3.00 4.00 5.00 Shaded area is beyond recommended range Frequency (MHz) Typical 2.7 mA @ 4 MHz, 5.5V FIGURE 18-15:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 20 pF, -40°C TO +85°C) 3500 6.0V 3000 5.5V 5.0V 2500 IDD(µA) Data based on process characterization samples. See first page of this section for details. 2.00 4.5V 4.0V 2000 3.
PIC16C9XX FIGURE 18-16:TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25°C) 1400 6.0V 5.5V 1200 5.0V 4.5V 1000 4.0V IDD(µA) 3.5V 800 3.0V 2.5V 600 400 200 0 600 800 1000 1200 1400 1600 Frequency (kHz) FIGURE 18-17:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40°C TO +85°C) 1600 6.0V 5.5V 1400 5.0V 4.5V 1200 4.0V 3.5V 1000 IDD(µA) 3.0V 2.5V 800 600 400 200 0 0 200 400 Shaded area is beyond recommended range 1997 Microchip Technology Inc.
PIC16C9XX FIGURE 18-18:TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25°C) 1200 6.0V 5.5V 1000 5.0V 4.5V 800 4.0V IDD(µA) 3.5V 600 3.0V 2.5V 400 200 0 0 100 200 300 400 500 600 700 FIGURE 18-19:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40°C TO +85°C) 1400 6.0V 1200 5.5V 5.0V 4.5V 1000 4.0V 3.5V 800 IDD(µA) Data based on process characterization samples. See first page of this section for details. Frequency (kHz) 3.0V 2.
PIC16C9XX TABLE 18-1: RC OSCILLATOR FREQUENCIES FIGURE 18-20:TRANSCONDUCTANCE(gm) OF HS OSCILLATOR vs. VDD Average Cext Rext 4.0 Fosc @ 5V, 25°C 100 pF 300 pF 5k 4.12 MHz ± 1.4% 10k 2.35 MHz ± 1.4% 3.0 100k 268 kHz ± 1.1% 2.5 3.3k 1.80 MHz ± 1.0% 5k 1.27 MHz ± 1.0% 10k 688 kHz ± 1.2% 100k 77.2 kHz ± 1.0% 3.3k 707 kHz ± 1.4% 5k 501 kHz ± 1.2% 10k 269 kHz ± 1.6% 100k 28.3 kHz ± 1.
PIC16C9XX FIGURE 18-23:TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25°C) FIGURE 18-26:TYPICAL IDD vs. VDD (LP MODE @ 25°C) 3.5 140 3.0 120 100 200 kHz, 15 pF/15 pF 2.0 80 32 kHz, 33 pF/33 pF 1.5 60 IDD(µA) Startup Time(Seconds) 2.5 1.0 0.5 200 kHz, 15 pF/15 pF 0.0 2.5 40 20 32 kHz, 33 pF/33 pF 3.0 3.5 4.0 4.5 5.0 5.5 0 2.5 6.0 VDD (VOLTS) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (VOLTS) FIGURE 18-24:TYPICAL XTAL STARTUP TIME vs. VDD (HS MODE, 25°C) LC Spec -> Typical = 22.
PIC16C9XX FIGURE 18-28:TYPICAL IDD vs. VDD (XT MODE @ 25°C) FIGURE 18-30:TYPICAL IDD vs. VDD (HS MODE @ 25°C) 7 1600 1400 6 1200 5 4 MHz, 15 pF/15 pF IDD(µA) 1000 800 1 MHz, 15 pF/15 pF IDD(µA) 600 8 MHz, 15 pF/15 pF 3 2 400 200 1 200 kHz, 33 pF/33 pF 0 2.5 4 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 4.0 VDD (VOLTS) 4.5 5.0 5.5 6.0 VDD (VOLTS) Typical = 2.7 µA, 4 MHz, 5.5V Typical = 3.5 mA, 8 MHz, 5.5V FIGURE 18-29:MAXIMUM IDD vs.
PIC16C9XX NOTES: DS30444E - page 170 1997 Microchip Technology Inc.
PIC16C9XX 19.0 PACKAGING INFORMATION 19.1 64-Lead Plastic Surface Mount (TQFP 10x10x1 mm Body 1.0/0.10 mm Lead Form)) D1 D D/2 e/2 A E1 E A DETAIL A e E/2 See Detail A 8 Places 11/13° 0° min. A See Detail B A2 Datum Plane 0.25 b with Lead Finish 0.09/0.20 0.08 R min. A1 0-7° Gauge Plane 0.20 min. 0.09/0.16 L 1.00 ref. b1 Base Metal DETAIL B Package Group: Plastic TQFP Millimeters Inches Symbol Min Nominal Max Min Nominal Max α A A1 A2 b b1 D D1 E E1 e L N 0° 0.05 0.95 0.
PIC16C9XX 19.2 64-Lead Plastic Dual In-line (750 mil) N α E1 E C eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A2 A e1 B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max α 0° A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 – 0.51 3.38 0.38 .076 0.20 57.40 55.12 19.05 16.76 1.73 19.05 19.05 3.05 64 1.19 0.686 DS30444E - page 172 Inches Notes Min Max 15° 0° 15° 5.08 – 4.27 0.56 1.27 0.30 57.91 55.12 19.69 17.27 1.83 19.05 21.08 3.
PIC16C9XX 19.3 68-Lead Plastic Leaded Chip Carrier (Square) D -A- D1 -D- 3 -F- 0.812/0.661 N Pics .032/.026 1.27 .050 2 Sides 0.177 .007 S B D-E S -HA A1 3 D3/E3 D2 0.38 .015 3 -G- 8 F-G S 0.177 .007 S B A S 2 Sides 9 0.101 Seating .004 Plane D -C- 4 E2 E1 E 0.38 .015 F-G S 4 -B- 3 -E- 0.177 .007 S A F-G S 10 0.254 .010 Max 2 0.254 .010 Max 11 -H- 11 0.508 .020 0.508 .020 -H- 2 0.812/0.661 3 .032/.026 1.524 .060 Min 6 6 -C1.651 .065 1.651 .065 R 1.14/0.64 .045/.
PIC16C9XX 19.4 Package Marking Information 68-Lead CERQUAD Windowed MMMMMMMMMMMMMMMMM Example PIC16C924-04/CL 9650CAE AABBCDE 64-Lead TQFP Example MMMMMMMMMM MMMMMMM PIC16C923 -08I/PT AABBCDE 9712CAE 68-Lead PLCC Example MMMMMMMMMM MMMMMMM PIC16C924 -08/L AABBCDE 9648CAE 64-Lead SDIP (Shrink DIP) Example MMMMMMMMMMMMMMMMM PIC16C924-04I/SP AABBCDE 9736CAE Legend: MM...M XX...
PIC16C9XX APPENDIX A: APPENDIX B: COMPATIBILITY The following are the list of modifications over the PIC16C5X microcontroller family: To convert code written for PIC16C5X to PIC16CXX, the user should take the following steps: 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (4K now as opposed to 512 before) and register file (192 bytes now versus 32 bytes before).
PIC16C9XX APPENDIX C: WHAT’S NEW 18 - TosH2ioL 200 ns Min (LC devices) Figure 13-13 (Resistor Ladder and Charge Pump) in LCD Section. 30 - TmcL 2 µs Min 34 - Tioz 2.1 µs Max Parameter D150 - Open Drain High Voltage. Timer0 and Timer1 External Clock Timings - Various. DC and AC Characterization Graphs and Tables. 53 - TccR, 54 - TccF APPENDIX D: WHAT’S CHANGED Various descriptions for clarity. Example code for Changing prescaler assignment between Timer0 and the WDT.
PIC16C9XX INDEX A A/D Accuracy/Error ............................................................ 86 ADCON0 ............................................................... 79, 80 ADCON1 ............................................................... 79, 80 ADIF............................................................................ 80 Analog-to-Digital Converter......................................... 79 Configuring Analog Port.............................................. 83 Connection Considerations.
PIC16C9XX Direct Addressing................................................................ 30 E Electrical Characteristics................................................... 141 External Power-on Reset Circuit ....................................... 112 F Family of Devices PIC16C9XX................................................................... 6 FSR ................................................................................... 108 FSR Register...............................................
PIC16C9XX PICMASTER In-Circuit Emulator ................................... 137 PICSTART Plus Entry Level Development System ....... 137 PIE1 .................................................................................. 113 PIE1 Register........................................................ 20, 26, 102 Pin Functions MCLRVPP.................................................................... 12 OSC1/CLKIN............................................................... 12 OSC2/CLKOUT..................
PIC16C9XX Special Function Registers, Section ................................... 19 SPI Master Mode ............................................................... 66 Serial Clock ................................................................. 65 Serial Data In .............................................................. 65 Serial Data Out ........................................................... 65 Serial Peripheral Interface (SPI) ................................. 63 Slave Select ..................
PIC16C9XX List of Equations And Examples Figure 8-1: Example 3-1: Example 4-1: Example 4-2: Example 5-1: Example 5-2: Example 5-3: Example 5-4: Example 5-5: Example 5-6: Example 5-7: Example 5-8: Figure 8-2: Figure 9-1: Figure 9-2: Instruction Pipeline Flow............................. 15 Call of a Subroutine in Page 1 from Page 0 30 Indirect Addressing ..................................... 30 Initializing PORTA....................................... 31 Initializing PORTB................................
PIC16C9XX Figure 14-4: Figure 14-5: Figure 14-6: Figure 14-7: Figure 14-8: Figure 14-9: Figure 14-10: Figure 14-11: Figure 14-12: Figure 14-13: Figure 14-14: Figure 14-15: Figure 14-16: Figure 14-17: Figure 14-18: Figure 14-19: Figure 15-1: Figure 17-1: Figure 17-2: Figure 17-3: Figure 17-4: Figure 17-5: Figure 17-6: Figure 17-7: Figure 17-8: Figure 17-9: Figure 17-10: Figure 17-11: Figure 17-12: Figure 17-13: Figure 17-14: Figure 18-1: Figure 18-2: Figure 18-3: Figure 18-4: Figure 18-5: Figure 18-6: Figur
PIC16C9XX Table 8-2: Table 9-1: Table 10-1: Table 10-2: Table 10-3: Table 10-4: Table 11-1: Table 11-2: Table 11-3: Table 11-4: Table 12-1: Table 12-2: Table 13-1: Table 13-2: Table 13-3: Table 13-4: Table 14-1: Table 14-2: Table 14-3: Table 14-4: Table 14-5: Table 14-6: Table 15-1: Table 15-2: Table 16-1: Table 17-1: Table 17-2: Table 17-3: Table 17-4: Table 17-5: Table 17-6: Table 17-7: Table 17-8: Table 17-9: Table 17-10: Table 17-11: Table 17-12: Table 17-13: Table 18-1: Registers Associated with Ti
PIC16C9XX DS30444E - page 184 1997 Microchip Technology Inc.
PIC16C9XX ON-LINE SUPPORT Microchip provides two methods of on-line support. These are the Microchip BBS and the Microchip World Wide Web (WWW) site. Use Microchip's Bulletin Board Service (BBS) to get current information and help about Microchip products. Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts.
PIC16C9XX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
PIC16C9XX PIC16C9XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. Examples PART NO.
Note the following details of the code protection feature on PICmicro® MCUs. • • • • • • The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature.
M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Microchip Technology Japan K.K.
