Datasheet

PIC16C77X
DS30275B-page 70 Advance Information  1999-2013 Microchip Technology Inc.
8.2.3 SLEEP OPERATION
While in sleep mode, the I
2
C module can receive
addresses or data, and when an address match or
complete byte transfer occurs wake the processor from
sleep (if the SSP interrupt is enabled).
8.2.4 EFFECTS OF A RESET
A reset diables the SSP module and terminates the
current transfer.
TABLE 8-3 REGISTERS ASSOCIATED WITH I
2
C OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh
INTCON GIE PEIE
T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1
PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1
PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Dh PIR2
LV D IF — — —BCLIF — — CCP2IF 0--- 0--0 0--- 0--0
8Dh PIE2
LV D IE — — —BCLIE — — CCP2IE 0--- 0--0 0--- 0--0
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
91h SSPCON2 GCEN AKSTAT AKDT AKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A
PS R/WUA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in I
2
C mode.
Note 1: These bits are reserved on the 28-pin devices, always maintain these bits clear.
2: These bits are reserved on these devices, always maintain these bits clear.
774.book Page 70 Tuesday, January 29, 2013 12:02 PM