Datasheet

PIC16C77X
 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 65
8.2.1.2 SLAVE RECEPTION
When the R/W
bit of the address byte is clear and an
address match occurs, the R/W
bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK
) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
TABLE 8-2 DATA TRANSFER RECEIVED BYTE ACTIONS
8.2.1.3 SLAVE TRANSMISSION
When the R/W
bit of the incoming address byte is set
and an address match occurs, the R/W
bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK
pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then the
SCL pin should be enabled by setting bit CKP (SSP-
CON<4>). The master must monitor the SCL pin prior
to asserting another clock pulse. The slave devices
may be holding off the master by stretching the clock.
The eight data bits are shifted out on the falling edge of
the SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 8-13).
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software,
and the SSPSTAT register is used to determine the sta-
tus of the byte tranfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
As a slave-transmitter, the ACK
pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK
), then the
data transfer is complete. When the not ACK
is latched
by the slave, the slave logic is reset and the slave then
monitors for another occurrence of the START bit. If the
SDA line was low (ACK
), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Then the SCL pin should be enabled
by setting the CKP bit.
FIGURE 8-12: I
2
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Note: The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occured. The ACK
is not sent and the SSP-
BUF is updated.
Status Bits as Data
Transfer is Received
SSPSR
SSPBUF
Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF SSPOV
00 Yes Yes Yes
10 No No Yes
11 No No Yes
0 1 Ye s No Ye s
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
P
9
8
76
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4
A3 A2 A1SDA
SCL
12
3
4
5
6
7
8
9
12
3
4
56
7
89
123
4
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK
Receiving Data
Receiving Data
D0
D1
D2
D3D4
D5
D6D7
ACK
R/W=0
Receiving Address
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
ACK
ACK is not sent.
Not
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