Datasheet

PIC16C77X
 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 63
8.2 MSSP I
2
C Operation
The MSSP module in I
2
C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on start and stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit address-
ing.
Refer to Application Note AN578,
"Use of the SSP
Module in the I
2
C Multi-Master Environment."
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independant of device frequency.
FIGURE 8-10: I
2
C SLAVE MODE BLOCK
DIAGRAM
FIGURE 8-11: I
2
C MASTER MODE BLOCK
DIAGRAM
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins that are automatically
configured when the I
2
C mode is enabled. The SSP
module functions are enabled by setting SSP Enable
bit SSPEN (SSPCON<5>).
The MSSP module has six registers for I
2
C operation.
They are the:
• SSP Control Register (SSPCON)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
sible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I
2
C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
2
C modes to be selected:
•I
2
C Slave mode (7-bit address)
•I
2
C Slave mode (10-bit address)
•I
2
C Master mode, clock = OSC/4 (SSPADD +1)
Before selecting any I
2
C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
ate TRIS bits. Selecting an I
2
C mode, by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I
2
C mode.
Read Write
SSPSR reg
Match detect
SSPADD reg
Start and
Stop bit detect
SSPBUF reg
Internal
data bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
SCL
shift
clock
MSb
LSb
SDA
Read Write
SSPSR reg
Match detect
SSPADD reg
Start and Stop bit
detect / generate
SSPBUF reg
Internal
data bus
Addr Match
Set/Clear S bit
Clear/Set P bit
(SSPSTAT reg)
SCL
shift
clock
MSb
LSb
SDA
Baud Rate Generator
7
SSPADD<6:0>
and
and Set SSPIF
774.book Page 63 Tuesday, January 29, 2013 12:02 PM