Datasheet

PIC16C77X
 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 55
FIGURE 8-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit
W = Writable bit
- n = Value at POR reset
bit7 bit0
bit 7: WCOL: Write Collision Detect bit
Master Mode:
1 = A write to the SSPBUF register was attempted while the I
2
C conditions were not valid for a
transmission to be started
0 = No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6: SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in slave mode. In slave mode, the user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode, the overflow bit is not
set since each new reception (and transmission) is initiated by writing to the SSPBUF register. (Must be
cleared in software).
0 = No overflow
In I
2
C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care"
in transmit mode. (Must be cleared in software).
0 = No overflow
bit 5: SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
2
C mode
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4: CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
2
C slave mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
In I
2
C master mode
Unused in this mode
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = F
OSC/4
0001 = SPI master mode, clock = F
OSC/16
0010 = SPI master mode, clock = F
OSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS
pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS
pin control disabled. SS can be used as I/O pin
0110 = I
2
C slave mode, 7-bit address
0111 = I
2
C slave mode, 10-bit address
1000 = I
2
C master mode, clock = FOSC / (4 * (SSPADD+1) )
1xx1 = Reserved
1x1x = Reserved
774.book Page 55 Tuesday, January 29, 2013 12:02 PM