Datasheet

PIC16C77X
 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 47
7.0 CAPTURE/COMPARE/PWM
(CCP) MODULE(S)
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Tab le 7- 1 shows the
timer resources of the CCP module modes.
The operation of CCP1 is identical to that of CCP2, with
the exception of the special trigger. Therefore, opera-
tion of a CCP module in the following sections is
described with respect to CCP1.
Ta ble 7 - 2 shows the interaction of the CCP modules.
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
CCP2 Module
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
Additional information on the CCP module is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
TABLE 7-1 CCP MODE - TIMER
RESOURCE
TABLE 7-2 INTERACTION OF TWO CCP MODULES
FIGURE 7-1: CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh)
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time-base.
Capture Compare The compare should be configured for the special event trigger, which clears TMR1.
Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1.
PWM PWM The PWMs will have the same frequency, and update rate (TMR2 interrupt).
PWM Capture None
PWM Compare None
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1
and starts an A/D conversion (if A/D module is enabled))
11xx = PWM mode
774.book Page 47 Tuesday, January 29, 2013 12:02 PM