Datasheet

PIC16C77X
DS30275B-page 46 Advance Information  1999-2013 Microchip Technology Inc.
6.2 Timer2 Interrupt
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is ini-
tialized to FFh upon reset.
6.3 Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
FIGURE 6-2: TIMER2 BLOCK DIAGRAM
TABLE 6-1 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Comparator
TMR2
Sets flag
TMR2 reg
output
(1)
Reset
Postscaler
Prescaler
PR2 reg
2
F
OSC/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1: TMR2 register output can be software selected
by the SSP Module as a baud clock.
to
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value o n:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh
INTCON GIE PEIE
T0IE INTE RBIE T0IF INTF RBIF
0000 000x 0000 000u
0Ch PIR1
PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
0000 0000 0000 0000
8Ch PIE1
PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
0000 0000 0000 0000
11h TMR2 Timer2 module’s register
0000 0000 0000 0000
12h T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000 -000 0000
92h PR2 Timer2 Period Register
1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: These bits are reserved on the 28-pin, always maintain these bits clear.
774.book Page 46 Tuesday, January 29, 2013 12:02 PM