Datasheet

PIC16C77X
DS30275B-page 30 Advance Information  1999-2013 Microchip Technology Inc.
The RB3 pin is multiplexed with analog channel 9 and
the low voltage detect input (RB3/AN9/LVDIN)
FIGURE 3-7: BLOCK DIAGRAM OF
RB3/AN9/LVDIN PIN
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 3-8: BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
RBPU
(2)
P
V
DD
QD
CK
QD
CK
QD
EN
Data bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
To A/D converter and LVD reference input
I/O
pin
(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to V
DD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU
bit (OPTION_REG<7>).
TRIS Latch
Analog
input mode
or LVD input
mode
Data Latch
From other
RBPU
(2)
P
V
DD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pins
weak
pull-up
RD Port
Latch
TTL
Input
Buffer
pin
(1)
Note 1: I/O pins have diode protection to VDD and VSS.
ST
Buffer
RB7:RB6 in serial programming mode
Q3
Q1
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU
bit (OPTION_REG<7>).
774.book Page 30 Tuesday, January 29, 2013 12:02 PM