Datasheet

PIC16C77X
 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 29
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, i.e., put
the contents of the output latch on the selected pin.
EXAMPLE 3-1: INITIALIZING PORTB
BCF STATUS, RP0 ;
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU
(OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
The RB0 pin is multiplexed with the external interrupt
(RB0/INT).
FIGURE 3-4: BLOCK DIAGRAM OF RB0 PIN
The RB1 pin is multiplexed with the SSP module slave
select (RB1/SS
).
FIGURE 3-5: BLOCK DIAGRAM OF RB1/SS
PIN
The RB2 pin is multiplexed with analog channel 8
(RB2/AN8).
FIGURE 3-6: BLOCK DIAGRAM OF
RB2/AN8 PIN
Data Latch
RBPU
(2)
P
V
DD
QD
CK
QD
CK
QD
EN
Data bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
RB0/INT
I/O
pin
(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to V
DD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU
bit (OPTION_REG<7>).
Schmitt Trigger
Buffer
TRIS Latch
Data Latch
RBPU
(2)
P
V
DD
QD
CK
QD
CK
QD
EN
Data bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
SS input
I/O
pin
(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to V
DD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU
bit (OPTION_REG<7>).
Schmitt Trigger
Buffer
TRIS Latch
Data Latch
RBPU
(2)
P
V
DD
QD
CK
QD
CK
QD
EN
Data bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
To A/D converter
I/O
pin
(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to V
DD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU
bit (OPTION_REG<7>).
TRIS Latch
Analog
input mode
774.book Page 29 Tuesday, January 29, 2013 12:02 PM