Datasheet

PIC16C77X
DS30275B-page 28 Advance Information  1999-2013 Microchip Technology Inc.
FIGURE 3-2: BLOCK DIAGRAM OF
RA1:RA0 AND RA5 PINS
FIGURE 3-3: BLOCK DIAGRAM OF
RA4/T0CKI PIN
TABLE 3-1 PORTA FUNCTIONS
TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Data
bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Por t
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
V
SS
VDD
I/O pin
(1)
Note 1: I/O pins have protection diodes to VDD and
V
SS.
Analog
input
mode
TTL
input
buffer
To A / D Co nv er t er
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Tr ig ge r
input
buffer
N
V
SS
I/O pin
(1)
TMR0 clock input
Note 1: I/O pin has protection diodes to V
SS only.
QD
Q
CK
QD
Q
CK
EN
QD
EN
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or analog input0
RA1/AN1 bit1 TTL Input/output or analog input1
RA2/AN2/V
REF-/VRL bit2 TTL Input/output or analog input2 or VREF- input or internal reference
voltage low
RA3/AN3/V
REF+/VRH bit3 TTL Input/output or analog input or VREF+ input or output of internal
reference voltage high
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0
Output is open drain type
RA5/AN4
(1)
bit5 TTL Input/output or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: RA5 is reserved on the 28-pin devices, maintain this bit clear.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
05h PORTA
(1)
— — RA5RA4RA3RA2RA1RA0--0x 0000 --0u 0000
85h TRISA
(1)
— — PORTA Data Direction Register --11 1111 --11 1111
9Fh ADCON1
ADFM VCFG2 VCFG1 VCFG0PCFG3PCFG2PCFG1PCFG00000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: PORTA<5>, TRISA<5> are reserved on the 28-pin devices, maintain these bits clear.
774.book Page 28 Tuesday, January 29, 2013 12:02 PM