Datasheet

PIC16C77X

DS30275B-page 22 Advance Information  1999-2013 Microchip Technology Inc.

2.2.2.7 PIR2 REGISTER

This register contains the CCP2, SSP Bus Collision,

and Low-voltage detect interrupt flag bits.

FIGURE 2-9: PIR2 REGISTER (ADDRESS 0Dh)

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0

LV DI F

— — —BCLIF — — CCP2IF R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: LV D I F: Low-voltage Detect Interrupt Flag bit

1 = The supply voltage has fallen below the specified LVD voltage (must be cleared in software)

0 = The supply voltage is greater than the specified LVD voltage

bit 6-4: Unimplemented: Read as '0'

bit 3: BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision has occurred while the SSP module configured in I

C Master was transmitting

(must be cleared in software)

0 = No bus collision occurred

bit 2-1: Unimplemented: Read as '0'

bit 0: CCP2IF: CCP2 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused

774.book Page 22 Tuesday, January 29, 2013 12:02 PM