Datasheet

PIC16C77X
 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 19
2.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 2-6: PIE1 REGISTER (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: PSPIE
(1)
: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6: ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5: RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4: TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2: CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on the 28-pin devices, always maintain this bit clear.
774.book Page 19 Tuesday, January 29, 2013 12:02 PM