Datasheet

PIC16C77X
 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 167
FIGURE 15-10: A/D CONVERSION TIMING (SLEEP MODE)
TABLE 15-11 A/D CONVERSION REQUIREMENTS
Parameter
No.
Sym Characteristic Min Typ† Max Units Conditions
130* T
AD A/D clock period 1.6 — — sVREF 2.5V
TBD — — sV
REF full range
130* T
AD A/D Internal RC
oscillator period 3.0 6.0 9.0 s
ADCS1:ADCS0 = 11 (RC mode)
At V
DD = 3.0V
2.0 4.0 6.0 sAt V
DD = 5.0V
131* T
CNV Conversion time (not
including acquisition
time)(Note 1)
—13T
AD ——
132* T
ACQ Acquisition Time Note 2
5*
11.5
—
—
—
s
s The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e
1mV @ 4.096V) from the last sam-
pled voltage (as stated on C
HOLD).
134* T
GO Q4 to A/D clock start — TOSC/2 + TCY — — If the A/D clock source is selected
as RC, a time of T
CY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following T
CY cycle.
2: See Section 11.6 for minimum conditions.
131
130
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
973210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
134
6
8
132
774.book Page 167 Tuesday, January 29, 2013 12:02 PM