Datasheet

PIC16C77X
DS30275B-page 166 Advance Information  1999-2013 Microchip Technology Inc.
FIGURE 15-9: A/D CONVERSION TIMING (NORMAL MODE)
TABLE 15-10 A/D CONVERSION REQUIREMENTS
Parameter
No.
Sym Characteristic Min Typ† Max Units Conditions
130* T
AD A/D clock period 1.6 — — s Tosc based, VREF 2.5V
3.0 — — s Tosc based, V
REF full range
130* T
AD A/D Internal RC
oscillator period 3.0 6.0 9.0 s
ADCS1:ADCS0 = 11 (RC mode)
At V
DD = 2.5V
2.0 4.0 6.0 sAt V
DD = 5.0V
131* T
CNV Conversion time (not
including
acquisition time)
(Note 1)
—13T
AD —TAD Set GO bit to new data in A/D result
register
132* T
ACQ Acquisition Time Note 2
5*
11.5
—
—
—
s
s The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e
1mV @ 4.096V) from the last sam-
pled voltage (as stated on C
HOLD).
134* T
GO Q4 to A/D clock start — TOSC/2 — — If the A/D clock source is selected
as RC, a time of T
CY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following T
CY cycle.
2: See Section 11.6 for minimum conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
987 3210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1/2 Tcy
6
134
774.book Page 166 Tuesday, January 29, 2013 12:02 PM