Datasheet

PIC16C77X
 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 15
Bank 2
100h
(4)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
102h
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
103h
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
104h
(4)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx 11xx uuuu 11uu
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Ch-
10Fh
— Unimplemented — —
Bank 3
180h
(4)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
181h OPTION_REG RBPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
182h
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
183h
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
184h
(4)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah
(1,4)
PCLATH — — —
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
18Bh
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
18Ch-
18Fh
— Unimplemented — —
TABLE 2-1 PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to
the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR
and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: These registers/bits are not implemented on the 28-pin devices read as '0'.
774.book Page 15 Tuesday, January 29, 2013 12:02 PM