Datasheet

PIC16C77X
DS30275B-page 14 Advance Information  1999-2013 Microchip Technology Inc.
Bank 1
80h
(4)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_REG RBPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
84h
(4)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA
— —bit5
(5)
PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h
(5)
TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h
(5)
TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
8Ah
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE
(3)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 LVDIE
— — —BCLIE— —CCP2IE0--- 0--0 0--- 0--0
8Eh PCON
— — — — — —PORBOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h SSPCON2 GCEN AKSTAT AKDT AKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I
2
C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 0000 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC
—BRGHTRMTTX9D0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN
— — — — 0000 ---- 0000 ----
9Ch LVDCON
— — BGST LVDEN LV3 LV2 LV1 LV0 --00 0101 --00 0101
9Ah — Unimplemented — —
9Eh ADRESL A/D Low Byte Result Register xxxx xxxx uuuu uuuu
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
TABLE 2-1 PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to
the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR
and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: These registers/bits are not implemented on the 28-pin devices read as '0'.
774.book Page 14 Tuesday, January 29, 2013 12:02 PM