Datasheet
PIC16C77X
1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 13
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Tab le 2- 1.
The special function registers can be classified into two
sets; core (CPU) and peripheral. Those registers asso-
ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1 PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Bank 0
00h
(4)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
04h
(4)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA
— —PORTA5
(5)
PORTA Data Latch when written: PORTA<4:0> pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx 11xx uuuu 11uu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h
(5)
PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
09h
(5)
PORTE — — — — —RE2RE1RE0---- -000 ---- -000
0Ah
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(3)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 LVDIF
— — –BCLIF— —CCP2IF0--- 0--0 0--- 0--0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON
— — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRESH A/D High Byte Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
CHS3 ADON 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to
the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR
and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: These registers/bits are not implemented on the 28-pin devices read as '0'.
774.book Page 13 Tuesday, January 29, 2013 12:02 PM