Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 28 8-Bit 20 MHz I/O number 22

 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 1

Microcontroller Core Features:

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program

branches which are two cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• 4K x 14 words of Program Memory,

256 x 8 bytes of Data Memory (RAM)

• Interrupt capability (up to 14 internal/external

interrupt sources)

• Eight level deep hardware stack

• Direct, indirect, and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and

Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• Low-power, high-speed CMOS EPROM

technology

• Fully static design

• In-Circuit Serial Programming(ISCP

• Wide operating voltage range: 2.5V to 5.5V

• High Sink/Source Current 25/25 mA

• Commercial and Industrial temperature ranges

• Low-power consumption:

- < 2 mA @ 5V, 4 MHz

-22.5 A typical @ 3V, 32 kHz

-< 1 A typical standby current

Pin Diagram

Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler,

can be incremented during sleep via external

crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period

• Two Capture, Compare, PWM modules

• Capture is 16-bit, max. resolution is 12.5 ns,

Compare is 16-bit, max. resolution is 200 ns,

PWM max. resolution is 10-bit

• 12-bit multi-channel Analog-to-Digital converter

• On-chip absolute bandgap voltage reference

generator

• Synchronous Serial Port (SSP) with SPI



(Master

Mode) and I



• Universal Synchronous Asynchronous Receiver

Transmitter, supports high/low speeds and 9-bit

address mode (USART/SCI)

• Parallel Slave Port (PSP) 8-bits wide, with

external RD

, WR and CS controls

• Programmable Brown-out detection circuitry for

Brown-out Reset (BOR)

• Programmable Low-voltage detection circuitry

600 mil. PDIP, Windowed CERDIP

RB7

RB6

RB5

RB4

RB3/AN9/LVDIN

RB2/AN8

RB1/SS

RB0/INT

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

MCLR/VPP

RA0/AN0

RA1/AN1

RA2/AN2/V

REF-/VRL

RA3/AN3/V

REF+/VRH

RA4/T0CKI

RA5/AN4

RE0/RD

/AN5

RE1/WR

/AN6

RE2/CS

/AN7

AVSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0

RD1/PSP1

PIC16C774

PIC16C77X

28/40-Pin, 8-Bit CMOS Microcontrollers w/ 12-Bit A/D

Enhanced features

774.book Page 1 Tuesday, January 29, 2013 12:02 PM

Summary of content (202 pages)

PAGE 1
774.book Page 1 Tuesday, January 29, 2013 12:02 PM PIC16C77X 28/40-Pin, 8-Bit CMOS Microcontrollers w/ 12-Bit A/D Microcontroller Core Features: Pin Diagram * Enhanced features  1999-2013 Microchip Technology Inc. 600 mil.
PAGE 2
774.book Page 2 Tuesday, January 29, 2013 12:02 PM PIC16C77X Pin Diagrams 300 mil.
PAGE 3
774.
PAGE 4
774.book Page 4 Tuesday, January 29, 2013 12:02 PM PIC16C77X Table of Contents 1.0 Device Overview ............................................................................................................................................................................ 5 2.0 Memory Organization................................................................................................................................................................... 11 3.0 I/O Ports .................................
PAGE 5
774.book Page 5 Tuesday, January 29, 2013 12:02 PM PIC16C77X 1.0 DEVICE OVERVIEW There a two devices (PIC16C773 and PIC16C774) covered by this datasheet. The PIC16C773 devices come in 28-pin packages and the PIC16C774 devices come in 40-pin packages. The 28-pin devices do not have a Parallel Slave Port implemented. This document contains device-specific information.
PAGE 6
774.
PAGE 7
74.book Page 7 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 1-1 PIC16C773 PINOUT DESCRIPTION Pin Name DIP, SSOP, SOIC Pin# I/O/P Type Buffer Type Description ST/CMOS(3) Oscillator crystal input/external clock source input. OSC1/CLKIN 9 I OSC2/CLKOUT 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
PAGE 8
774.book Page 8 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 1-2 PIC16C774 PINOUT DESCRIPTION Pin Name DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type ST/CMOS Description (4) Oscillator crystal input/external clock source input. OSC1/CLKIN 13 14 30 I OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
PAGE 9
774.book Page 9 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 1-2 PIC16C774 PINOUT DESCRIPTION (Cont.’d) DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1 output.
PAGE 10
774.book Page 10 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 10 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 11
774.book Page 11 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.0 MEMORY ORGANIZATION There are two memory blocks in each of these PICmicro ® microcontrollers. Each block (Program Memory and Data Memory) has its own bus so that concurrent access can occur. Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual, (DS33023). 2.1 Program Memory Organization The PIC16C77X PICmicros have a 13-bit program counter capable of addressing an 8K x 14 program memory space.
PAGE 12
774.book Page 12 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 2-2: REGISTER FILE MAP File Address Indirect addr.
PAGE 13
774.book Page 13 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2 SPECIAL FUNCTION REGISTERS The special function registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in that peripheral feature section.
PAGE 14
774.book Page 14 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 2-1 PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.
PAGE 15
774.book Page 15 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 2-1 PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.
PAGE 16
774.book Page 16 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.1 STATUS REGISTER For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). The STATUS register, shown in Figure 2-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.
PAGE 17
774.book Page 17 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.2 OPTION_REG REGISTER Note: The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 2-4: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PAGE 18
774.book Page 18 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.3 INTCON REGISTER Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. FIGURE 2-5: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PAGE 19
774.book Page 19 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the peripheral interrupts. FIGURE 2-6: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PAGE 20
774.book Page 20 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the peripheral interrupts. FIGURE 2-7: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PAGE 21
774.book Page 21 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.6 PIE2 REGISTER This register contains the individual enable bits for the CCP2, SSP bus collision, and low voltage detect interrupts.
PAGE 22
774.book Page 22 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.7 PIR2 REGISTER . Note: This register contains the CCP2, SSP Bus Collision, and Low-voltage detect interrupt flag bits. FIGURE 2-9: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PAGE 23
774.book Page 23 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.8 PCON REGISTER Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. BOR is unknown on Power-on Reset.
PAGE 24
774.book Page 24 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.3 PCL and PCLATH 2.4 The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register. 2.3.
PAGE 25
774.book Page 25 Tuesday, January 29, 2013 12:02 PM PIC16C77X EXAMPLE 2-1: The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).
PAGE 26
774.book Page 26 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 26 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 27
774.book Page 27 Tuesday, January 29, 2013 12:02 PM PIC16C77X 3.0 I/O PORTS FIGURE 3-1: Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023). Data bus WR Port BLOCK DIAGRAM OF RA3:RA2 PINS D Q VDD CK Q P Data Latch 3.
PAGE 28
774.
PAGE 29
774.book Page 29 Tuesday, January 29, 2013 12:02 PM PIC16C77X 3.2 PORTB and the TRISB Register The RB1 pin is multiplexed with the SSP module slave select (RB1/SS). PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, i.e.
PAGE 30
774.book Page 30 Tuesday, January 29, 2013 12:02 PM PIC16C77X The RB3 pin is multiplexed with analog channel 9 and the low voltage detect input (RB3/AN9/LVDIN) FIGURE 3-7: BLOCK DIAGRAM OF RB3/AN9/LVDIN PIN VDD RBPU(2) Data bus WR Port weak P pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q WR TRIS b) Q Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF.
PAGE 31
774.book Page 31 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 3-3 PORTB FUNCTIONS Name Bit# Buffer RB0/INT bit0 TTL/ST(1) Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1/SS bit1 TTL/ST(3) Input/output pin or SSP slave select. Internal software programmable weak pull-up. RB2/AN8 bit2 TTL Input/output pin or analog input8. Internal software programmable weak pull-up.
PAGE 32
774.book Page 32 Tuesday, January 29, 2013 12:02 PM PIC16C77X 3.3 PORTC and the TRISC Register PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output, i.e., put the contents of the output latch on the selected pin.
PAGE 33
774.
PAGE 34
774.book Page 34 Tuesday, January 29, 2013 12:02 PM PIC16C77X 3.4 PORTD and TRISD Registers This section is applicable to the 40/44-pin devices only. FIGURE 3-10: PORTD BLOCK DIAGRAM (IN I/O PORT MODE) Data bus PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. WR PORT PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
PAGE 35
774.book Page 35 Tuesday, January 29, 2013 12:02 PM PIC16C77X 3.5 PORTE and TRISE Register FIGURE 3-11: PORTE BLOCK DIAGRAM (IN I/O PORT MODE) This section is applicable to the 40/44-pin devices only. Data bus PORTE has three pins RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers.
PAGE 36
774.book Page 36 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 3-9 PORTE FUNCTIONS Name Bit# Buffer Type Function (1) Input/output port pin or read control input in parallel slave port mode or analog input: RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected) Input/output port pin or write control input in parallel slave port mode or analog input: WR 1 = Not a write operation 0 = Write operation.
PAGE 37
774.book Page 37 Tuesday, January 29, 2013 12:02 PM PIC16C77X 3.6 Parallel Slave Port FIGURE 3-13: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) The Parallel Slave Port is implemented on the 40/44-pin devices only. PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In slave mode it is asynchronously readable and writable by the external world through RD control input pin RE0/RD and WR control input pin RE1/WR.
PAGE 38
774.
PAGE 39
774.book Page 39 Tuesday, January 29, 2013 12:02 PM PIC16C77X 4.0 TIMER0 MODULE Additional information on external clock requirements is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). The Timer0 module timer/counter has the following features: • • • • • • 4.
PAGE 40
774.book Page 40 Tuesday, January 29, 2013 12:02 PM PIC16C77X 4.2.1 4.3 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program execution. Note: The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>).
PAGE 41
774.book Page 41 Tuesday, January 29, 2013 12:02 PM PIC16C77X 5.0 TIMER1 MODULE 5.
PAGE 42
774.book Page 42 Tuesday, January 29, 2013 12:02 PM PIC16C77X 5.1.1 TIMER1 COUNTER OPERATION In this mode, Timer1 is being incremented via an external source. Increments occur on a rising edge. After Timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. FIGURE 5-2: TIMER1 INCREMENTING EDGE T1CKI (Default high) T1CKI (Default low) Note: Arrows indicate counter increments.
PAGE 43
774.book Page 43 Tuesday, January 29, 2013 12:02 PM PIC16C77X 5.2 Timer1 Oscillator 5.3 A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 5-1 shows the capacitor selection for the Timer1 oscillator.
PAGE 44
774.book Page 44 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 44 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 45
774.book Page 45 Tuesday, January 29, 2013 12:02 PM PIC16C77X 6.0 TIMER2 MODULE 6.1 The Timer2 module timer has the following features: • • • • • • • Timer2 Operation Timer2 can be used as the PWM time-base for PWM mode of the CCP module.
PAGE 46
774.book Page 46 Tuesday, January 29, 2013 12:02 PM PIC16C77X 6.2 Timer2 Interrupt FIGURE 6-2: Sets flag bit TMR2IF The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon reset. 6.
PAGE 47
774.book Page 47 Tuesday, January 29, 2013 12:02 PM PIC16C77X 7.0 CAPTURE/COMPARE/PWM (CCP) MODULE(S) CCP2 Module Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 7-1 shows the timer resources of the CCP module modes. The operation of CCP1 is identical to that of CCP2, with the exception of the special trigger.
PAGE 48
774.book Page 48 Tuesday, January 29, 2013 12:02 PM PIC16C77X 7.1 Capture Mode 7.1.4 In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software.
PAGE 49
774.book Page 49 Tuesday, January 29, 2013 12:02 PM PIC16C77X 7.2 Compare Mode 7.2.1 In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • driven High • driven Low • remains Unchanged Note: 7.2.2 The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set.
PAGE 50
774.book Page 50 Tuesday, January 29, 2013 12:02 PM PIC16C77X 7.3 PWM Mode 7.3.1 In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch.
PAGE 51
774.book Page 51 Tuesday, January 29, 2013 12:02 PM PIC16C77X 7.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
PAGE 52
774.book Page 52 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 52 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 53
774.book Page 53 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PAGE 54
774.
PAGE 55
774.
PAGE 56
774.book Page 56 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-3: R/W-0 GCEN bit7 SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h) R/W-0 AKSTAT R/W-0 AKDT R/W-0 AKEN R/W-0 RCEN R/W-0 PEN R/W-0 RSEN R/W-0 SEN bit0 R =Readable bit W =Writable bit U =Unimplemented bit, Read as ‘0’ - n =Value at POR reset bit 7: GCEN: General Call Enable bit (In I2C slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR. 0 = General call address disabled.
PAGE 57
774.book Page 57 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.1 SPI Mode FIGURE 8-4: The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported.
PAGE 58
774.book Page 58 Tuesday, January 29, 2013 12:02 PM PIC16C77X determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 8-1 shows the loading of the SSPBUF (SSPSR) for data transmission.
PAGE 59
774.book Page 59 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.1.4 Figure 8-6, Figure 8-8, and Figure 8-9 where the MSb is transmitted first. In master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 8-5) is to broadcast data by the software protocol.
PAGE 60
774.book Page 60 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.1.5 SLAVE MODE In slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched the interrupt flag bit SSPIF (PIR1<3>) is set. While in slave mode the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications.
PAGE 61
774.
PAGE 62
774.book Page 62 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.1.7 8.1.8 SLEEP OPERATION EFFECTS OF A RESET A reset disables the MSSP module and terminates the current transfer. In master mode all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from sleep. After the device returns to normal mode, the module will continue to transmit/ receive data. In slave mode, the SPI transmit/receive shift register operates asynchronously to the device.
PAGE 63
774.book Page 63 Tuesday, January 29, 2013 12:02 PM PIC16C77X MSSP I 2C Operation 8.2 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing.
PAGE 64
774.book Page 64 Tuesday, January 29, 2013 12:02 PM PIC16C77X The SSPSTAT register gives the status of the data transfer. This information includes detection of a START (S) or STOP (P) bit, specifies if the received byte was data or address if the next byte is the completion of 10-bit address, and if this will be a read or write data transfer. SSPBUF is the register to which the transfer data is written to or read from. The SSPSR register shifts the data in or out of the device.
PAGE 65
774.book Page 65 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.1.2 SLAVE RECEPTION An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the received byte. When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register.
PAGE 66
774.
PAGE 67
 1999-2013 Microchip Technology Inc. S 1 Advance Information UA (SSPSTAT<1>) 2 1 4 1 5 0 6 7 A9 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 8 9 ACK Receive First Byte of Address R/W = 0 1 BF (SSPSTAT<0>) (PIR1<3>) SSPIF SCL SDA 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated.
PAGE 68
DS30275B-page 68 S 1 1 Advance Information UA (SSPSTAT<1>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF SCL SDA 2 1 3 1 5 0 6 A9 7 A8 UA is set indicating that the SSPADD needs to be updated 8 9 ACK R/W = 0 SSPBUF is written with contents of SSPSR 4 1 Receive First Byte of Address 1 3 A5 4 A4 Cleared in software 2 A6 5 A3 6 A2 7 A1 8 A0 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address.
PAGE 69
774.book Page 69 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.2 If the general call address matches, the SSPSR is transfered to the SSPBUF, the BF flag is set (eighth bit), and on the falling edge of the ninth bit (ACK bit) the SSPIF flag is set. GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the START condition usually determines which device will be the slave addressed by the master.
PAGE 70
774.book Page 70 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.3 8.2.4 SLEEP OPERATION 2 EFFECTS OF A RESET A reset diables the SSP module and terminates the current transfer. While in sleep mode, the I C module can receive addresses or data, and when an address match or complete byte transfer occurs wake the processor from sleep (if the SSP interrupt is enabled).
PAGE 71
774.book Page 71 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.5 In master mode, the SCL and SDA lines are manipulated by the MSSP hardware. MASTER MODE Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle with both the S and P bits clear.
PAGE 72
774.book Page 72 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.6 8.2.7.4 MULTI-MASTER OPERATION In multi-master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle with both the S and P bits clear.
PAGE 73
774.book Page 73 Tuesday, January 29, 2013 12:02 PM PIC16C77X i) The MSSP Module shifts in the ACK bit from the slave device, and writes its value into the SSPCON2 register ( SSPCON2<6>). The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. The user generates a STOP condition by setting the STOP enable bit PEN in SSPCON2. Interrupt is generated once the STOP condition is complete. j) k) l) 8.2.
PAGE 74
774.book Page 74 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.9 I2C MASTER MODE START CONDITION TIMING 8.2.9.5 If the user writes the SSPBUF when an START sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). To initiate a START condition, the user sets the start condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the baud rate generator is re-loaded with the contents of SSPADD<6:0>, and starts its count.
PAGE 75
774.book Page 75 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-21: START CONDITION FLOWCHART SSPEN = 1, SSPCON<3:0> = 1000 Idle Mode SEN (SSPCON2<0> = 1) Bus collision detected, Set BCLIF, Release SCL, Clear SEN No SDA = 1? SCL = 1? Yes Load BRG with SSPADD<6:0> No No No Yes SDA = 0? SCL= 0? Yes BRG Rollover? Yes Reset BRG Force SDA = 0, Load BRG with SSPADD<6:0>, Set S bit.
PAGE 76
774.book Page 76 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.10 I2C MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C module is in the idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the baud rate generator is loaded with the contents of SSPADD<6:0>, and begins counting. The SDA pin is released (brought high) for one baud rate generator count (TBRG).
PAGE 77
4.book Page 77 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-23: REPEATED START CONDITION FLOWCHART (PAGE 1) Start Idle Mode, SSPEN = 1, SSPCON<3:0> = 1000 B RSEN = 1 Force SCL = 0 No SCL = 0? Yes Release SDA, Load BRG with SSPADD<6:0> BRG rollover? No Yes Release SCL (Clock Arbitration) SCL = 1? No Yes Bus Collision, Set BCLIF, Release SDA, Clear RSEN No SDA = 1? Yes Load BRG with SSPADD<6:0> C  1999-2013 Microchip Technology Inc.
PAGE 78
774.book Page 78 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-24: REPEATED START CONDITION FLOWCHART (PAGE 2) B C A Yes No No No SDA = 0? SCL = 1? Yes BRG rollover? Yes Reset BRG Force SDA = 0, Load BRG with SSPADD<6:0> Set S No SCL = '0'? Yes Reset BRG DS30275B-page 78 Advance Information No BRG rollover? Yes Force SCL = 0, Repeated Start condition done, Clear RSEN, Set SSPIF.  1999-2013 Microchip Technology Inc.
PAGE 79
774.book Page 79 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.11 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or either half of a 10-bit address is accomplished by simply writing a value to SSPBUF register. This action will set the buffer full flag (BF) and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time spec).
PAGE 80
774.
PAGE 81
 1999-2013 Microchip Technology Inc. S Advance Information R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 cleared in software 2 6 7 8 9 After start condition SEN cleared by hardware.
PAGE 82
774.book Page 82 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.12 I2C MASTER MODE RECEPTION 8.2.12.10 BF STATUS FLAG Master mode reception is enabled by programming the receive enable bit, RCEN (SSPCON2<3>). Note: The SSP Module must be in an IDLE STATE before the RCEN bit is set, or the RCEN bit will be disregarded. The baud rate generator begins counting, and on each rollover, the state of the SCL pin changes (high to low/ low to high) and data is shifted into the SSPSR.
PAGE 83
774.book Page 83 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-27: MASTER RECEIVER FLOWCHART Idle mode RCEN = 1 Num_Clocks = 0, Release SDA Force SCL=0, Load BRG w/ SSPADD<6:0>, start count BRG rollover? No Yes Release SCL (Clock Arbitration) SCL = 1? No Yes Sample SDA, Shift data into SSPSR Load BRG with SSPADD<6:0>, start count. BRG rollover? No Yes SCL = 0? No Yes Num_Clocks = Num_Clocks + 1 No Num_Clocks = 8? Yes Force SCL = 0, Set SSPIF, Set BF.
PAGE 84
DS30275B-page 84 S Advance Information AKEN SSPOV BF (SSPSTAT<0>) SDA = 0, SCL = 1 while CPU responds to SSPIF SSPIF SCL SDA 1 A7 2 4 5 Cleared in software 3 6 A6 A5 A4 A3 A2 Transmit Address to Slave SEN = 0 Write to SSPBUF occurs here Start XMIT Write to SSPCON2<0> (SEN = 1) Begin Start Condition 7 A1 8 9 R/W = 1 ACK ACK from Slave 2 3 5 6 7 8 D0 9 ACK 2 3 4 5 6 7 Cleared in software Set SSPIF interrupt at end of acknowledge sequence Data shifted in on falling edg
PAGE 85
774.book Page 85 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.13 ACKNOWLEDGE SEQUENCE TIMING rate generator counts for TBRG . The SCL pin is then pulled low. Following this, the AKEN bit is automatically cleared, the baud rate generator is turned off, and the SSP module then goes into IDLE mode. (Figure 829) An acknowledge sequence is enabled by setting the acknowledge sequence enable bit, AKEN (SSPCON2<4>).
PAGE 86
774.book Page 86 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-30: ACKNOWLEDGE FLOWCHART Idle mode Set AKEN Force SCL = 0 BRG rollover? Yes No No SCL = 0? Yes Yes Drive AKDT bit (SSPCON2<5>) onto SDA pin, Load BRG with SSPADD<6:0>, start count.
PAGE 87
774.book Page 87 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.14 STOP CONDITION TIMING while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later the PEN bit is cleared and the SSPIF bit is set (Figure 8-31). A stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit PEN (SSPCON2<2>). At the end of a receive/transmit the SCL line is held low after the falling edge of the ninth clock.
PAGE 88
774.
PAGE 89
774.book Page 89 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.15 CLOCK ARBITRATION 8.2.16 Clock arbitration occurs when the master, during any receive, transmit, or repeated start/stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high.
PAGE 90
774.book Page 90 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.18 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA by letting SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be stable.
PAGE 91
774.book Page 91 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.18.15 BUS COLLISION DURING A START CONDITION During a START condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the START condition (Figure 8-35). SCL is sampled low before SDA is asserted low. (Figure 8-36). b) During a START condition both the SDA and the SCL pins are monitored.
PAGE 92
774.book Page 92 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-36: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, Bus collision occurs, Set BCLIF. SEN SCL = 0 before BRG time out, Bus collision occurs, Set BCLIF. BCLIF Interrupts cleared in software.
PAGE 93
774.book Page 93 Tuesday, January 29, 2013 12:02 PM PIC16C77X however SDA is sampled high then the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs, because no two masters can assert SDA at exactly the same time. 8.2.18.16 BUS COLLISION DURING A REPEATED START CONDITION During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level.
PAGE 94
774.book Page 94 Tuesday, January 29, 2013 12:02 PM PIC16C77X The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allow to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data '0'.
PAGE 95
774.book Page 95 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.3 Connection Considerations for I2C Bus For standard-mode I2C bus devices, the values of resistors Rp Rs in Figure 8-42 depends on the following parameters example, with a supply voltage of VDD = 5V+10% and VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 = 1.7 k VDD as a function of Rp is shown in Figure 8-42. The desired noise margin of 0.1VDD for the low level limits the maximum value of Rs.
PAGE 96
774.book Page 96 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 96 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 97
774.book Page 97 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to be set in order to configure pins RC6/TX/CK and RC7/ RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter.
PAGE 98
774.
PAGE 99
774.book Page 99 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.1 USART Baud Rate Generator (BRG) EXAMPLE 9-1: The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In asynchronous mode bit BRGH (TXSTA<2>) also controls the baud rate. In synchronous mode bit BRGH is ignored.
PAGE 100
774.book Page 100 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 9-3 BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR SYNCHRONOUS MODE FOSC = 20 MHz KBAUD % ERROR NA NA NA NA 19.53 76.92 96.15 294.1 500 5000 19.53 +1.73 +0.16 +0.16 -1.96 0 - 16 MHz SPBRG value KBAUD (decimal) 255 64 51 16 9 0 255 FOSC = 5.0688 MHz BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW +0.16 +0.16 -0.79 +2.
PAGE 101
774.book Page 101 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 9-5 BAUD RATE (K) 9.6 19.2 38.4 57.6 115.2 250 625 1250 BAUD RATE (K) BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz KBAUD % ERROR 9.615 19.230 37.878 56.818 113.636 250 625 1250 +0.16 +0.16 -1.36 -1.36 -1.36 0 0 0 16 MHz SPBRG value (decimal) KBAUD 129 64 32 21 10 4 1 0 9.615 19.230 38.461 58.823 111.111 250 NA NA 10 MHz SPBRG % value ERROR (decimal) KBAUD +0.16 +0.16 +0.16 +2.12 -3.55 0 - 103 51 25 16 8 3 - 9.
PAGE 102
774.book Page 102 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.2 USART Asynchronous Mode (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE ( PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register.
PAGE 103
774.book Page 103 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 9-4: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG output (shift clock) RC6/TX/CK (pin) Start Bit Bit 0 Bit 1 Stop Bit WORD 1 Transmit Shift Reg TRMT bit (Transmit shift reg. empty flag) FIGURE 9-5: Bit 7/8 WORD 1 TXIF bit (Transmit buffer reg. empty flag) ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 BRG output (shift clock) RC6/TX/CK (pin) Start Bit TXIF bit (interrupt reg.
PAGE 104
774.book Page 104 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.2.2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 9-6. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. The USART module has a special provision for multiprocessor communication.
PAGE 105
774.
PAGE 106
774.book Page 106 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 9-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST Start bit RC7/RX/DT (pin) bit0 bit1 bit8 Stop bit Start bit bit0 bit8 Stop bit Load RSR Bit8 = 1, Address Byte Bit8 = 0, Data Byte WORD 1 RCREG Read RCIF Note: This timing diagram shows an address byte followed by a data byte. The data byte is not read into the RCREG (receive buffer) because ADEN was not updated and still = 0.
PAGE 107
774.book Page 107 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner i.e. transmission and reception do not occur at the same time. When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>).
PAGE 108
774.book Page 108 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 9-9: SYNCHRONOUS TRANSMISSION Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4Q1 Q2 Q3Q4 RC7/RX/DT pin Bit 0 Bit 1 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Bit 2 Bit 7 Bit 0 Bit 1 Bit 7 WORD 2 WORD 1 RC6/TX/CK pin Write to TXREG reg Write word1 Write word2 TXIF bit (Interrupt flag) TRMT TRMT bit TXEN bit '1' '1' Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.
PAGE 109
774.book Page 109 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.3.2 3. 4. Ensure bits CREN and SREN are clear. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 8.
PAGE 110
774.book Page 110 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.4 USART Synchronous Slave Mode Synchronous slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 9.4.
PAGE 111
774.
PAGE 112
774.book Page 112 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 112 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 113
774.book Page 113 Tuesday, January 29, 2013 12:02 PM PIC16C77X 10.0 VOLTAGE REFERENCE MODULE AND LOW-VOLTAGE DETECT The source for the reference voltages comes from the bandgap reference circuit. The bandgap circuit is energized anytime the reference voltage is required by the other sub-modules, and is powered down when not in use. The control registers for this module are LVDCON and REFCON, as shown in Figure 10-1 and Figure 10-2.
PAGE 114
774.book Page 114 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 10-2: REFCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 VRHEN VRLEN VRHOEN VRLOEN — — — — bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: VRHEN: Voltage Reference High Enable bit (VRH = 4.
PAGE 115
774.book Page 115 Tuesday, January 29, 2013 12:02 PM PIC16C77X 10.3 Low-voltage Detect (LVD) This module is used to generate an interrupt when the supply voltage falls below a specified “trip” voltage. This module operates completely under software control. This allows a user to power the module on and off to periodically monitor the supply voltage, and thus minimize total current consumption.
PAGE 116
774.book Page 116 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 116 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 117
774.book Page 117 Tuesday, January 29, 2013 12:02 PM PIC16C77X 11.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has four registers. These registers are: • • • • The analog-to-digital (A/D) converter module has six inputs for the PIC16C773 and ten for the PIC16C774. The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 12-bit digital number. The A/D module has up to 10 analog inputs, which are multiplexed into one sample and hold.
PAGE 118
774.
PAGE 119
774.book Page 119 Tuesday, January 29, 2013 12:02 PM PIC16C77X The value that is in the ADRESH and ADRESL registers are not modified for a Power-on Reset. The ADRESH and ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 11.6.
PAGE 120
774.book Page 120 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 11-3: A/D BLOCK DIAGRAM CHS3:CHS0 RB3/AN9 RB2/AN8 RE2/AN7(1) RE1/AN6(1) VAIN RE0/AN5(1) (Input voltage) RA5/AN4(1) RA3/AN3/VREF+/VRH RA2/AN2/VREF-/VRL RA1/AN1 AVDD VREFH RA0/AN0 VRH VRL (Reference voltage) VCFG2:VCFG0 A/D Converter VREFL VRL (Reference voltage) AVSS VCFG2:VCFG0 Note 1: Not available on 28-pin devices. DS30275B-page 120 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 121
774.book Page 121 Tuesday, January 29, 2013 12:02 PM PIC16C77X 11.4 Selecting the A/D Conversion Clock The A/D conversion cycle requires 13TAD: 1 TAD for settling time, and 12 TAD for conversion. The source of the A/D conversion clock is software selected. The four possible options for TAD are: • • • • 2 TOSC 8 TOSC 32 TOSC Internal RC oscillator TABLE 11-1 2 TOSC 8 TOSC 32 TOSC RC For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s.
PAGE 122
774.
PAGE 123
774.book Page 123 Tuesday, January 29, 2013 12:02 PM PIC16C77X 11.6 A/D Sample Requirements 11.6.1 RECOMMENDED SOURCE IMPEDANCE The maximum recommended impedance for analog sources is 2.5 k. This value is calculated based on the maximum leakage current of the input pin. The leakage current is 100 nA max., and the analog input voltage cannot be vary by more than 1/4 LSb or 250 mV due to leakage. This places a requirement on the input impedance of 250 V/100 nA = 2.5 k. 11.6.
PAGE 124
774.book Page 124 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 11-7: CALCULATING THE MINIMUM REQUIRED SAMPLE TIME TACQ = TACQ = TC = TC = TC = TC = TC = TC = Amplifier Settling Time + Holding Capacitor Charging Time +Temperature Coefficient † 5 s + TC + [(Temp - 25C)(0.05s/C)] † + Holding Capacitor Charging Time (CHOLD) (RIC + RSS + RS) In (1/16384) -25 pF (1 k +10 k + 2.5 k) In (1/16384) -25 pF (13.5 k) In (1/16384) -0.338 (-9.704)s 3.3s TACQ = 5s + 3.3 s + [(50C - 25C)(0.
PAGE 125
774.book Page 125 Tuesday, January 29, 2013 12:02 PM PIC16C77X 11.7 Use of the CCP Trigger 11.9 An A/D conversion can be started by the “special event trigger” of the CCP module. This requires that the CCPnM<3:0> bits be programmed as 1011b and that the A/D module is enabled (ADON is set). When the trigger occurs, the GO/DONE bit will be set on Q2 to start the A/D conversion and the Timer1 counter will be reset to zero.
PAGE 126
774.book Page 126 Tuesday, January 29, 2013 12:02 PM PIC16C77X 11.10 A/D Operation During Sleep Turning off the A/D places the A/D module in its lowest current consumption state. The A/D module can operate during SLEEP mode. This requires that the A/D clock source be configured for RC (ADCS1:ADCS0 = 11b). With the RC clock source selected, when the GO/DONE bit is set the A/D module waits one instruction cycle before starting the conversion cycle.
PAGE 127
774.book Page 127 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.0 SPECIAL FEATURES OF THE CPU These PICmicro devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PAGE 128
774.
PAGE 129
774.book Page 129 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 12-2: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) C1(1) OSC1 XTAL C2 Note1: 2: 3: To internal logic RF(3) RS(2) PIC16C77X See Table 12-1 and Table 12-2 for recommended values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the crystal chosen. PIC16C77X Open TABLE 12-1 OSC2 CERAMIC RESONATORS Ranges Tested: Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.
PAGE 130
774.book Page 130 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.2.3 RC OSCILLATOR For timing insensitive applications the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation.
PAGE 131
774.book Page 131 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.3 Reset The PIC16C77X devices have several different resets. These resets are grouped into two classifications; power-up and non-power-up. The power-up type resets are the power-on and brown-out resets which assume the device VDD was below its normal operating range for the device’s configuration. The non-power up type resets assume normal operating limits were maintained before/during and after the reset.
PAGE 132
774.book Page 132 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.4 Power-On Reset (POR) 12.5 A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. For a slow rise time, see Figure 12-6.
PAGE 133
774.book Page 133 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.8 Time-out Sequence Table 12-5 shows the reset conditions for some special function registers, while Table 12-6 shows the reset conditions for all the registers. On power-up the time-out sequence is as follows: First PWRT time-out is invoked by the POR pulse. When the PWRT delay expires the Oscillator Start-up Timer is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT.
PAGE 134
774.
PAGE 135
774.book Page 135 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 12-6 INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.
PAGE 136
774.
PAGE 137
774.book Page 137 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.10 Interrupts The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The PIC16C77X family has up to 14 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits.
PAGE 138
774.book Page 138 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.10.1 INT INTERRUPT 12.10.3 PORTB INTCON CHANGE External interrupt on RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>).
PAGE 139
774.book Page 139 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.12 Watchdog Timer (WDT) The WDT can be permanently disabled by clearing configuration bit WDTE (Section 12.1). The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin.
PAGE 140
774.book Page 140 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.13 Power-down Mode (SLEEP) Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present. Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off.
PAGE 141
774.book Page 141 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 12-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = SLEEP Instruction executed Inst(PC - 1) Note 1: 2: 3: 4: 12.14 PC+1 PC+2 Inst(PC + 2) SLEEP Inst(PC + 1) 12.
PAGE 142
774.book Page 142 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 142 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 143
774.book Page 143 Tuesday, January 29, 2013 12:02 PM PIC16C77X 13.0 INSTRUCTION SET SUMMARY Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 13-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 13-1 shows the opcode field descriptions.
PAGE 144
774.
PAGE 145
774.book Page 145 Tuesday, January 29, 2013 12:02 PM PIC16C77X 14.0 DEVELOPMENT SUPPORT 14.
PAGE 146
774.book Page 146 Tuesday, January 29, 2013 12:02 PM PIC16C77X 14.6 SIMICE Entry-Level Hardware Simulator 14.8 PICDEM-2 Low-Cost PIC16CXX Demonstration Board SIMICE is an entry-level hardware development system designed to operate in a PC-based environment with Microchip’s simulator MPLAB™-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology’s MPLAB Integrated Development Environment (IDE) software.
PAGE 147
774.book Page 147 Tuesday, January 29, 2013 12:02 PM PIC16C77X 14.10 MPLAB Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: • A full featured editor • Three operating modes - editor - emulator - simulator • A project manager • Customizable tool bar and key mapping • A status bar with project information • Extensive on-line help 14.
PAGE 148
774.book Page 148 Tuesday, January 29, 2013 12:02 PM PIC16C77X 14.16 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters. DS30275B-page 148 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 149
Emulator Products Software Tools  1999-2013 Microchip Technology Inc.
PAGE 150
774.book Page 150 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 150 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 151
774.book Page 151 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias................................................................................................................ .-55 to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR.
PAGE 152
774.book Page 152 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.1 DC Characteristics: PIC16C77X (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units Conditions D001 D001A Supply Voltage VDD 4.0 4.5 — — 5.5 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR — 1.
PAGE 153
774.book Page 153 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.2 DC Characteristics:PIC16LC77X-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units Conditions D001 Supply Voltage VDD 2.5 — 5.5 V D002* RAM Data Retention Voltage (Note 1) VDR — 1.
PAGE 154
774.book Page 154 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.3 DC Characteristics: PIC16C77X (Commercial, Industrial) DC CHARACTERISTICS Param No.
PAGE 155
774.book Page 155 Tuesday, January 29, 2013 12:02 PM PIC16C77X DC CHARACTERISTICS Param No. Characteristic D090 Output High Voltage I/O ports (Note 3) D092 OSC2/CLKOUT (RC osc config) D150* Open-Drain High Voltage Capacitive Loading Specs on Output Pins OSC2 pin D100 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2.
PAGE 156
774.book Page 156 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.4 DC Characteristics: VREF TABLE 15-2 ELECTRICAL CHARACTERISTICS: VREF DC CHARACTERISTICS Param No. D400 D401A D401B D402 D404 D405 D406 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2.
PAGE 157
774.book Page 157 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-1: LOW-VOLTAGE DETECT CHARACTERISTICS VDD VLHYS VLVD (LVDIF set by hardware) LVDIF (LVDIF can be cleared in software anytime during the gray area) TABLE 15-3 ELECTRICAL CHARACTERISTICS: LVD DC CHARACTERISTICS Param No.
PAGE 158
774.book Page 158 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-2: BROWN-OUT RESET CHARACTERISTICS VDD (device not in Brown-out Reset) VBHYS VBOR (device in Brown-out Reset) RESET (due to BOR) TABLE 15-4 72 ms time out ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param No. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 15.
PAGE 159
774.book Page 159 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.5 AC Characteristics: PIC16C77X (Commercial, Industrial) 15.5.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PAGE 160
774.book Page 160 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-3: LOAD CONDITIONS Load condition 1 Load condition 2 VDD/2 RL CL Pin CL Pin VSS VSS RL = 464 CL = 50 pF 15 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16C773. DS30275B-page 160 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 161
774.book Page 161 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.5.2 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 15-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKOUT TABLE 15-5 Parameter No.
PAGE 162
774.book Page 162 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-5: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 15-3 for load conditions. TABLE 15-6 CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No.
PAGE 163
774.book Page 163 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 15-3 for load conditions. FIGURE 15-7: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 15-7 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER,POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No.
PAGE 164
774.book Page 164 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-8: BANDGAP START-UP TIME VBGAP = 1.2V VBGAP Enable Bandgap TBGAP Bandgap stable TABLE 15-8 BANDGAP START-UP TIME Parameter No. Sym 36* TBGAP * † Characteristic Bandgap start-up time Min Typ† Max Units Conditions — 30 TBD s Defined as the time between the instant that the bandgap is enabled and the moment that the bandgap reference voltage is stable. These parameters are characterized but not tested.
PAGE 165
774.book Page 165 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 15-9 Param No. Sym A01 NR A03 A/D CONVERTER CHARACTERISTICS: Characteristic Min Typ† Max Units Conditions Resolution — — 12 bits bit Min. resolution for A/D is 1 mV, VREF+ = AVDD = 4.096V, VREF- = AVSS = 0V, VREF-  VAIN  VREF+ EIL Integral error — — +/-2 LSb — VREF+ = AVDD = 4.
PAGE 166
774.book Page 166 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-9: A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 1/2 Tcy 134 131 Q4 130 A/D CLK 9 A/D DATA 8 7 6 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE 132 SAMPLE Note 1: SAMPLING STOPPED If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 15-10 A/D CONVERSION REQUIREMENTS Parameter No.
PAGE 167
774.book Page 167 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-10: A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO 134 131 Q4 130 A/D CLK 9 A/D DATA 8 7 6 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 15-11 A/D CONVERSION REQUIREMENTS Parameter No.
PAGE 168
774.book Page 168 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-11: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 15-3 for load conditions. TABLE 15-12 TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width 41* 42* 45* 46* 47* 48 * † Min No Prescaler With Prescaler No Prescaler With Prescaler T0CKI Low Pulse Width Max Units Conditions 0.
PAGE 169
774.book Page 169 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-12: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 15-3 for load conditions. TABLE 15-13 Parameter No.
PAGE 170
774.book Page 170 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-13: PARALLEL SLAVE PORT TIMING (PIC16C774) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 15-3 for load conditions. TABLE 15-14 Parameter No.
PAGE 171
774.book Page 171 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 15-3 for load conditions. TABLE 15-15 Param No.
PAGE 172
774.book Page 172 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 172 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 173
774.book Page 173 Tuesday, January 29, 2013 12:02 PM PIC16C77X 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
PAGE 174
774.book Page 174 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 174 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 175
774.book Page 175 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.0 PACKAGING INFORMATION 17.
PAGE 176
774.
PAGE 177
774.book Page 177 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.2 K04-070 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PAGE 178
774.book Page 178 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.3 K04-080 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PAGE 179
774.book Page 179 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.4 K04-052 28-Lead Plastic Small Outline (SO) – Wide, 300 mil Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 E p D B 2 1 n X  45 ° L R2 c A  Units Dimension Limits Pitch Number of Pins Overall Pack.
PAGE 180
774.book Page 180 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.5 K04-073 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 E p D B 2 1 n  L A R2 c A1 R1  A2 L1  Units Dimension Limits Pitch Number of Pins Overall Pack.
PAGE 181
774.book Page 181 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.6 K04-016 40-Lead Plastic Dual In-line (P) – 600 mil Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PAGE 182
774.book Page 182 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.7 K04-014 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PAGE 183
774.book Page 183 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.8 K04-076 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.1 mm Lead Form Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 E # leads = n1 p D D1 2 1 B n X x 45° L  A R2 c  L1 R1  Units Dimension Limits Pitch Number of Pins Pins along Width Overall Pack.
PAGE 184
774.book Page 184 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.9 K04-071 44-Lead Plastic Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 E # leads = n1 p D D1 2 1 B n X x 45°  L R2 c A R1   L1 Units Dimension Limits Pitch Number of Pins Pins along Width Overall Pack.
PAGE 185
774.book Page 185 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.10 K04-048 44-Lead Plastic Leaded Chip Carrier (L) – Square Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 E # leads = n1 D D1 n 12 CH2 x 45°  A3 CH1 x 45° R1 L 35° A1 R2  c A B1 B A2 p E2 Units Dimension Limits Number of Pins Pitch Overall Pack. Height Shoulder Height Standoff Side 1 Chamfer Dim.
PAGE 186
774.book Page 186 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 186 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 187
774.book Page 187 Tuesday, January 29, 2013 12:02 PM PIC16C77X APPENDIX A: REVISION HISTORY Version Date Revision Description A 1999 This is a new data sheet. However, the devices described in this data sheet are the upgrades to the devices found in the PIC16C7X Data Sheet, DS30390E. B 2013 Added a note to each package drawing. APPENDIX B: DEVICE DIFFERENCES The differences between the devices in this data sheet are listed in Table B-1.
PAGE 188
774.book Page 188 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 188 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 189
774.book Page 189 Tuesday, January 29, 2013 12:02 PM PIC16C77X INDEX C A Capture (CCP Module) ...................................................... 48 Block Diagram ........................................................... 48 CCP Pin Configuration .............................................. 48 CCPR1H:CCPR1L Registers .................................... 48 Changing Between Capture Prescalers .................... 48 Software Interrupt ......................................................
PAGE 190
774.book Page 190 Tuesday, January 29, 2013 12:02 PM PIC16C77X E Errata ................................................................................... 4 External Power-on Reset Circuit ...................................... 132 F Firmware Instructions ....................................................... 143 Flowcharts Acknowledge .............................................................. 86 Master Receiver ......................................................... 83 Master Transmit ...........
PAGE 191
774.book Page 191 Tuesday, January 29, 2013 12:02 PM PIC16C77X Interrupts, Flag Bits A/D Converter Flag (ADIF Bit) ................................... 20 CCP1 Flag (CCP1IF Bit) ................................ 20, 48, 49 CCP2 Flag (CCP2IF Bit) ............................................ 22 Interrupt on Change (RB7:RB4) Flag (RBIF Bit) ..................................................... 18, 30, 138 PSP Read/Write Flag (PSPIF Bit) .............................. 20 RB0/INT Flag (INTF Bit) .................
PAGE 192
774.book Page 192 Tuesday, January 29, 2013 12:02 PM PIC16C77X RC4/SDI/SDA Pin .................................................... 7, 9 RC5/SDO Pin ........................................................... 7, 9 RC6/TX/CK Pin .................................................. 7, 9, 98 RC7/RX/DT Pin ............................................ 7, 9, 98, 99 TRISC Register .................................................... 32, 97 PORTC Register .............................................................
PAGE 193
774.book Page 193 Tuesday, January 29, 2013 12:02 PM PIC16C77X S SAE .................................................................................... 56 SCK .................................................................................... 57 SCL .................................................................................... 64 SDA .................................................................................... 64 SDI ..........................................................................
PAGE 194
774.book Page 194 Tuesday, January 29, 2013 12:02 PM PIC16C77X Overflow Interrupt ................................................ 41, 43 RC0/T1OSO/T1CKI Pin ........................................... 7, 9 RC1/T1OSI/CCP2 Pin .............................................. 7, 9 Special Event Trigger (CCP) ................................ 43, 49 T1CON Register ........................................................ 41 TMR1H Register ........................................................
PAGE 195
774.book Page 195 Tuesday, January 29, 2013 12:02 PM PIC16C77X W W Register ....................................................................... 138 Wake-up from SLEEP .............................................. 127, 140 Interrupts .......................................................... 133, 134 MCLR Reset ............................................................ 134 Timing Diagram ........................................................ 141 WDT Reset ...........................................
PAGE 196
774.book Page 196 Tuesday, January 29, 2013 12:02 PM PIC16C77X BIT/REGISTER CROSS-REFERENCE LIST ADCS1:ADCS0 ..................................ADCON0<7:6> ADIE ...................................................PIE1<6> ADIF ...................................................PIR1<6> ADON .................................................ADCON0<0> BF .......................................................SSPSTAT<0> BOR ...................................................PCON<0> BRGH ...........................
PAGE 197
774.book Page 197 Tuesday, January 29, 2013 12:02 PM PIC16C77X ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
PAGE 198
774.book Page 198 Tuesday, January 29, 2013 12:02 PM PIC16C77X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
PAGE 199
774.book Page 199 Tuesday, January 29, 2013 12:02 PM PIC16C77X PIC16C77X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X -XX Frequency Temperature Range Range /XX XXX Package Pattern Examples: g) h) Device PIC16C77X(1), PIC16C77XT(2);VDD range 4.0V to 5.5V PIC16LC77X(1), PIC16LC77XT(2);VDD range 2.5V to 5.5V Frequency Range 04 20 i) PIC16C774 -04/P 301 = Commercial temp.
PAGE 200
774.book Page 200 Tuesday, January 29, 2013 12:02 PM PIC16C77X DS30275B-page 200 Advance Information  1999-2013 Microchip Technology Inc.
PAGE 201
774.book Page 201 Tuesday, January 29, 2013 12:02 PM Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 202
774.book Page 202 Tuesday, January 29, 2013 12:02 PM Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.