Datasheet

PIC16C745/765
DS41124D-page 46 Preliminary  1999-2013 Microchip Technology Inc.
7.1 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FINT. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
7.2 Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
If T1SYNC
is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The pres-
caler however will continue to increment.
FIGURE 7-1: TIMER1 BLOCK DIAGRAM
TMR1H
TMR1L
T1OSC
T1SYNC
TMR1CS
T1CKPS<1:0>
SLEEP input
T1OSCEN
Enable
Oscillator
(1)
FINT
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
0
1
Synchronized
clock input
2
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
Set flag bit
TMR1IF on
Overflow
TMR1